drivers/gpu/drm/i915/display/intel_dram.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/i915/display/intel_dram.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/i915/display/intel_dram.c
Extension
.c
Size
19487 bytes
Lines
856
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct dram_dimm_info {
	u16 size;
	u8 width, ranks;
};

struct dram_channel_info {
	struct dram_dimm_info dimm_l, dimm_s;
	u8 ranks;
	bool is_16gb_dimm;
};

#define DRAM_TYPE_STR(type) [INTEL_DRAM_ ## type] = #type

const char *intel_dram_type_str(enum intel_dram_type type)
{
	static const char * const str[] = {
		DRAM_TYPE_STR(UNKNOWN),
		DRAM_TYPE_STR(DDR2),
		DRAM_TYPE_STR(DDR3),
		DRAM_TYPE_STR(DDR4),
		DRAM_TYPE_STR(LPDDR3),
		DRAM_TYPE_STR(LPDDR4),
		DRAM_TYPE_STR(DDR5),
		DRAM_TYPE_STR(LPDDR5),
		DRAM_TYPE_STR(GDDR),
		DRAM_TYPE_STR(GDDR_ECC),
	};

	BUILD_BUG_ON(ARRAY_SIZE(str) != __INTEL_DRAM_TYPE_MAX);

	if (type >= ARRAY_SIZE(str))
		type = INTEL_DRAM_UNKNOWN;

	return str[type];
}

#undef DRAM_TYPE_STR

static enum intel_dram_type pnv_dram_type(struct intel_display *display)
{
	return intel_mchbar_read(display, CSHRDDR3CTL) & CSHRDDR3CTL_DDR3 ?
		INTEL_DRAM_DDR3 : INTEL_DRAM_DDR2;
}

static unsigned int pnv_mem_freq(struct intel_display *display)
{
	u32 tmp;

	tmp = intel_mchbar_read(display, CLKCFG);

	switch (tmp & CLKCFG_MEM_MASK) {
	case CLKCFG_MEM_533:
		return 533333;
	case CLKCFG_MEM_667:
		return 666667;
	case CLKCFG_MEM_800:
		return 800000;
	}

	return 0;
}

static unsigned int ilk_mem_freq(struct intel_display *display)
{
	u16 ddrpll;

	ddrpll = intel_mchbar_read16(display, DDRMPLL1);
	switch (ddrpll & 0xff) {
	case 0xc:
		return 800000;
	case 0x10:
		return 1066667;
	case 0x14:
		return 1333333;
	case 0x18:
		return 1600000;
	default:
		drm_dbg_kms(display->drm, "unknown memory frequency 0x%02x\n",
			    ddrpll & 0xff);
		return 0;
	}
}

static unsigned int chv_mem_freq(struct intel_display *display)
{
	u32 val;

	vlv_cck_get(display);
	val = vlv_cck_read(display, CCK_FUSE_REG);
	vlv_cck_put(display);

Annotation

Implementation Notes