drivers/gpu/drm/i915/display/intel_dsi_vbt_defs.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/i915/display/intel_dsi_vbt_defs.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/i915/display/intel_dsi_vbt_defs.h
Extension
.h
Size
4140 bytes
Lines
198
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct mipi_config {
	u16 panel_id;

	/* General Params */
	struct {
		u32 enable_dithering:1;
		u32 rsvd1:1;
		u32 is_bridge:1;

		u32 panel_arch_type:2;
		u32 is_cmd_mode:1;

#define NON_BURST_SYNC_PULSE	0x1
#define NON_BURST_SYNC_EVENTS	0x2
#define BURST_MODE		0x3
		u32 video_transfer_mode:2;

		u32 cabc_supported:1;
#define PPS_BLC_PMIC   0
#define PPS_BLC_SOC    1
		u32 pwm_blc:1;

#define PIXEL_FORMAT_RGB565			0x1
#define PIXEL_FORMAT_RGB666			0x2
#define PIXEL_FORMAT_RGB666_LOOSELY_PACKED	0x3
#define PIXEL_FORMAT_RGB888			0x4
		u32 videomode_color_format:4;

#define ENABLE_ROTATION_0	0x0
#define ENABLE_ROTATION_90	0x1
#define ENABLE_ROTATION_180	0x2
#define ENABLE_ROTATION_270	0x3
		u32 rotation:2;
		u32 bta_disable:1;
		u32 rsvd2:15;
	} __packed;

	/* Port Desc */
	struct {
#define DUAL_LINK_NOT_SUPPORTED	0
#define DUAL_LINK_FRONT_BACK	1
#define DUAL_LINK_PIXEL_ALT	2
		u16 dual_link:2;
		u16 lane_cnt:2;
		u16 pixel_overlap:3;
		u16 rgb_flip:1;
#define DL_DCS_PORT_A			0x00
#define DL_DCS_PORT_C			0x01
#define DL_DCS_PORT_A_AND_C		0x02
		u16 dl_dcs_cabc_ports:2;
		u16 dl_dcs_backlight_ports:2;
		u16 port_sync:1;				/* 219-230 */
		u16 rsvd3:3;
	} __packed;

	/* DSI Controller Parameters */
	struct {
		u16 dsi_usage:1;
		u16 rsvd4:15;
	} __packed;

	u8 rsvd5;
	u32 target_burst_mode_freq;
	u32 dsi_ddr_clk;
	u32 bridge_ref_clk;

	/* LP Byte Clock */
	struct {
#define  BYTE_CLK_SEL_20MHZ		0
#define  BYTE_CLK_SEL_10MHZ		1
#define  BYTE_CLK_SEL_5MHZ		2
		u8 byte_clk_sel:2;
		u8 rsvd6:6;
	} __packed;

	/* DPhy Flags */
	struct {
		u16 dphy_param_valid:1;
		u16 eot_pkt_disabled:1;
		u16 enable_clk_stop:1;
		u16 blanking_packets_during_bllp:1;		/* 219+ */
		u16 lp_clock_during_lpm:1;			/* 219+ */
		u16 rsvd7:11;
	} __packed;

	u32 hs_tx_timeout;
	u32 lp_rx_timeout;
	u32 turn_around_timeout;
	u32 device_reset_timer;
	u32 master_init_timer;

Annotation

Implementation Notes