drivers/gpu/drm/i915/display/intel_fifo_underrun.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/i915/display/intel_fifo_underrun.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
Extension
.c
Size
18043 bytes
Lines
586
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

intel_de_read(display, GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) {
			drm_err(display->drm,
				"uncleared fifo underrun on pipe %c\n",
				pipe_name(pipe));
		}
	}
}

static void bdw_set_fifo_underrun_reporting(struct intel_display *display,
					    enum pipe pipe, bool enable)
{
	if (enable)
		bdw_enable_pipe_irq(display, pipe, GEN8_PIPE_FIFO_UNDERRUN);
	else
		bdw_disable_pipe_irq(display, pipe, GEN8_PIPE_FIFO_UNDERRUN);
}

static void ibx_set_fifo_underrun_reporting(struct intel_display *display,
					    enum pipe pch_transcoder,
					    bool enable)
{
	u32 bit = (pch_transcoder == PIPE_A) ?
		SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;

	if (enable)
		ibx_enable_display_interrupt(display, bit);
	else
		ibx_disable_display_interrupt(display, bit);
}

static void cpt_check_pch_fifo_underruns(struct intel_crtc *crtc)
{
	struct intel_display *display = to_intel_display(crtc);
	enum pipe pch_transcoder = crtc->pipe;
	u32 serr_int = intel_de_read(display, SERR_INT);

	lockdep_assert_held(&display->irq.lock);

	if ((serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) == 0)
		return;

	intel_de_write(display, SERR_INT,
		       SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
	intel_de_posting_read(display, SERR_INT);

	trace_intel_pch_fifo_underrun(display, pch_transcoder);
	drm_err(display->drm, "pch fifo underrun on pch transcoder %c\n",
		pipe_name(pch_transcoder));
}

static void cpt_set_fifo_underrun_reporting(struct intel_display *display,
					    enum pipe pch_transcoder,
					    bool enable, bool old)
{
	if (enable) {
		intel_de_write(display, SERR_INT,
			       SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));

		if (!cpt_can_enable_serr_int(display))
			return;

		ibx_enable_display_interrupt(display, SDE_ERROR_CPT);
	} else {
		ibx_disable_display_interrupt(display, SDE_ERROR_CPT);

		if (old && intel_de_read(display, SERR_INT) &
		    SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) {
			drm_err(display->drm,
				"uncleared pch fifo underrun on pch transcoder %c\n",
				pipe_name(pch_transcoder));
		}
	}
}

static bool __intel_set_cpu_fifo_underrun_reporting(struct intel_display *display,
						    enum pipe pipe, bool enable)
{
	struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
	bool old;

	lockdep_assert_held(&display->irq.lock);

	old = !crtc->cpu_fifo_underrun_disabled;
	crtc->cpu_fifo_underrun_disabled = !enable;

	/*
	 * The debug bits get latched at the time of the FIFO underrun ISR bit
	 * getting set.  That means that any non-zero debug bit that is read when
	 * handling a FIFO underrun interrupt has the potential to belong to
	 * another underrun event (past or future).  To alleviate this problem,

Annotation

Implementation Notes