drivers/gpu/drm/i915/display/intel_gmbus.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/i915/display/intel_gmbus.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/i915/display/intel_gmbus.c- Extension
.c- Size
- 27747 bytes
- Lines
- 1035
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/export.hlinux/i2c-algo-bit.hlinux/i2c.hlinux/iopoll.hdrm/drm_print.hdrm/display/drm_hdcp_helper.hintel_de.hintel_display_regs.hintel_display_types.hintel_display_wa.hintel_gmbus.hintel_gmbus_regs.hintel_parent.h
Detected Declarations
struct intel_gmbusstruct gmbus_pinenum gmbus_gpiofunction intel_gmbus_is_valid_pinfunction to_intel_gmbusfunction intel_gmbus_resetfunction pnv_gmbus_clock_gatingfunction pch_gmbus_clock_gatingfunction bxt_gmbus_clock_gatingfunction get_reservedfunction get_clockfunction get_datafunction set_clockfunction set_datafunction ptl_handle_mask_bitsfunction intel_gpio_pre_xferfunction intel_gpio_post_xferfunction intel_gpio_setupfunction has_gmbus_irqfunction gmbus_waitfunction gmbus_wait_idlefunction gmbus_max_xfer_sizefunction gmbus_xfer_read_chunkfunction gmbus_xfer_readfunction gmbus_xfer_write_chunkfunction gmbus_xfer_writefunction gmbus_is_index_xferfunction gmbus_index_xferfunction do_gmbus_xferfunction gmbus_xferfunction intel_gmbus_output_aksvfunction gmbus_funcfunction gmbus_lock_busfunction gmbus_trylock_busfunction gmbus_unlock_busfunction intel_gmbus_setupfunction intel_gmbus_force_bitfunction intel_gmbus_is_forced_bitfunction intel_gmbus_teardownfunction intel_gmbus_irq_handler
Annotated Snippet
struct intel_gmbus {
struct i2c_adapter adapter;
#define GMBUS_FORCE_BIT_RETRY (1U << 31)
u32 force_bit;
u32 reg0;
intel_reg_t gpio_reg;
struct i2c_algo_bit_data bit_algo;
struct intel_display *display;
};
enum gmbus_gpio {
GPIOA,
GPIOB,
GPIOC,
GPIOD,
GPIOE,
GPIOF,
GPIOG,
GPIOH,
__GPIOI_UNUSED,
GPIOJ,
GPIOK,
GPIOL,
GPIOM,
GPION,
GPIOO,
};
struct gmbus_pin {
const char *name;
enum gmbus_gpio gpio;
};
/* Map gmbus pin pairs to names and registers. */
static const struct gmbus_pin gmbus_pins[] = {
[GMBUS_PIN_SSC] = { "ssc", GPIOB },
[GMBUS_PIN_VGADDC] = { "vga", GPIOA },
[GMBUS_PIN_PANEL] = { "panel", GPIOC },
[GMBUS_PIN_DPC] = { "dpc", GPIOD },
[GMBUS_PIN_DPB] = { "dpb", GPIOE },
[GMBUS_PIN_DPD] = { "dpd", GPIOF },
};
static const struct gmbus_pin gmbus_pins_bdw[] = {
[GMBUS_PIN_VGADDC] = { "vga", GPIOA },
[GMBUS_PIN_DPC] = { "dpc", GPIOD },
[GMBUS_PIN_DPB] = { "dpb", GPIOE },
[GMBUS_PIN_DPD] = { "dpd", GPIOF },
};
static const struct gmbus_pin gmbus_pins_skl[] = {
[GMBUS_PIN_DPC] = { "dpc", GPIOD },
[GMBUS_PIN_DPB] = { "dpb", GPIOE },
[GMBUS_PIN_DPD] = { "dpd", GPIOF },
};
static const struct gmbus_pin gmbus_pins_bxt[] = {
[GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
[GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
[GMBUS_PIN_3_BXT] = { "misc", GPIOD },
};
static const struct gmbus_pin gmbus_pins_cnp[] = {
[GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
[GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
[GMBUS_PIN_3_BXT] = { "misc", GPIOD },
[GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
};
static const struct gmbus_pin gmbus_pins_icp[] = {
[GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
[GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
[GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
[GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
[GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
[GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
[GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
[GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION },
[GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO },
};
static const struct gmbus_pin gmbus_pins_dg1[] = {
[GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
[GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
[GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
[GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
};
static const struct gmbus_pin gmbus_pins_dg2[] = {
[GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
Annotation
- Immediate include surface: `linux/export.h`, `linux/i2c-algo-bit.h`, `linux/i2c.h`, `linux/iopoll.h`, `drm/drm_print.h`, `drm/display/drm_hdcp_helper.h`, `intel_de.h`, `intel_display_regs.h`.
- Detected declarations: `struct intel_gmbus`, `struct gmbus_pin`, `enum gmbus_gpio`, `function intel_gmbus_is_valid_pin`, `function to_intel_gmbus`, `function intel_gmbus_reset`, `function pnv_gmbus_clock_gating`, `function pch_gmbus_clock_gating`, `function bxt_gmbus_clock_gating`, `function get_reserved`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.