drivers/gpu/drm/i915/display/intel_hdcp_regs.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/i915/display/intel_hdcp_regs.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/i915/display/intel_hdcp_regs.h- Extension
.h- Size
- 10061 bytes
- Lines
- 273
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
intel_display_reg_defs.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef __INTEL_HDCP_REGS_H__
#define __INTEL_HDCP_REGS_H__
#include "intel_display_reg_defs.h"
#define TRANS_HDCP(__i915) (DISPLAY_VER(__i915) >= 12)
/* HDCP Key Registers */
#define HDCP_KEY_CONF _MMIO(0x66c00)
#define HDCP_AKSV_SEND_TRIGGER REG_BIT(31)
#define HDCP_CLEAR_KEYS_TRIGGER REG_BIT(30)
#define HDCP_KEY_LOAD_TRIGGER REG_BIT(8)
#define HDCP_KEY_STATUS _MMIO(0x66c04)
#define HDCP_FUSE_IN_PROGRESS REG_BIT(7)
#define HDCP_FUSE_ERROR REG_BIT(6)
#define HDCP_FUSE_DONE REG_BIT(5)
#define HDCP_KEY_LOAD_STATUS REG_BIT(1)
#define HDCP_KEY_LOAD_DONE REG_BIT(0)
#define HDCP_AKSV_LO _MMIO(0x66c10)
#define HDCP_AKSV_HI _MMIO(0x66c14)
/* HDCP Repeater Registers */
#define HDCP_REP_CTL _MMIO(0x66d00)
#define HDCP_TRANSA_REP_PRESENT REG_BIT(31)
#define HDCP_TRANSB_REP_PRESENT REG_BIT(30)
#define HDCP_TRANSC_REP_PRESENT REG_BIT(29)
#define HDCP_TRANSD_REP_PRESENT REG_BIT(28)
#define HDCP_DDIB_REP_PRESENT REG_BIT(30)
#define HDCP_DDIA_REP_PRESENT REG_BIT(29)
#define HDCP_DDIC_REP_PRESENT REG_BIT(28)
#define HDCP_DDID_REP_PRESENT REG_BIT(27)
#define HDCP_DDIF_REP_PRESENT REG_BIT(26)
#define HDCP_DDIE_REP_PRESENT REG_BIT(25)
#define HDCP_TRANSA_SHA1_M0 (1 << 20)
#define HDCP_TRANSB_SHA1_M0 (2 << 20)
#define HDCP_TRANSC_SHA1_M0 (3 << 20)
#define HDCP_TRANSD_SHA1_M0 (4 << 20)
#define HDCP_DDIB_SHA1_M0 (1 << 20)
#define HDCP_DDIA_SHA1_M0 (2 << 20)
#define HDCP_DDIC_SHA1_M0 (3 << 20)
#define HDCP_DDID_SHA1_M0 (4 << 20)
#define HDCP_DDIF_SHA1_M0 (5 << 20)
#define HDCP_DDIE_SHA1_M0 (6 << 20) /* Bspec says 5? */
#define HDCP_SHA1_BUSY REG_BIT(16)
#define HDCP_SHA1_READY REG_BIT(17)
#define HDCP_SHA1_COMPLETE REG_BIT(18)
#define HDCP_SHA1_V_MATCH REG_BIT(19)
#define HDCP_SHA1_TEXT_32 (1 << 1)
#define HDCP_SHA1_COMPLETE_HASH (2 << 1)
#define HDCP_SHA1_TEXT_24 (4 << 1)
#define HDCP_SHA1_TEXT_16 (5 << 1)
#define HDCP_SHA1_TEXT_8 (6 << 1)
#define HDCP_SHA1_TEXT_0 (7 << 1)
#define HDCP_SHA_V_PRIME_H0 _MMIO(0x66d04)
#define HDCP_SHA_V_PRIME_H1 _MMIO(0x66d08)
#define HDCP_SHA_V_PRIME_H2 _MMIO(0x66d0C)
#define HDCP_SHA_V_PRIME_H3 _MMIO(0x66d10)
#define HDCP_SHA_V_PRIME_H4 _MMIO(0x66d14)
#define HDCP_SHA_V_PRIME(h) _MMIO((0x66d04 + (h) * 4))
#define HDCP_SHA_TEXT _MMIO(0x66d18)
/* HDCP Auth Registers */
#define _PORTA_HDCP_AUTHENC 0x66800
#define _PORTB_HDCP_AUTHENC 0x66500
#define _PORTC_HDCP_AUTHENC 0x66600
#define _PORTD_HDCP_AUTHENC 0x66700
#define _PORTE_HDCP_AUTHENC 0x66A00
#define _PORTF_HDCP_AUTHENC 0x66900
#define _PORT_HDCP_AUTHENC(port, x) _MMIO(_PICK(port, \
_PORTA_HDCP_AUTHENC, \
_PORTB_HDCP_AUTHENC, \
_PORTC_HDCP_AUTHENC, \
_PORTD_HDCP_AUTHENC, \
_PORTE_HDCP_AUTHENC, \
_PORTF_HDCP_AUTHENC) + (x))
#define PORT_HDCP_CONF(port) _PORT_HDCP_AUTHENC(port, 0x0)
#define _TRANSA_HDCP_CONF 0x66400
#define _TRANSB_HDCP_CONF 0x66500
#define TRANS_HDCP_CONF(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_CONF, \
_TRANSB_HDCP_CONF)
#define HDCP_CONF(dev_priv, trans, port) \
(TRANS_HDCP(dev_priv) ? \
TRANS_HDCP_CONF(trans) : \
PORT_HDCP_CONF(port))
#define HDCP_CONF_CAPTURE_AN REG_BIT(0)
#define HDCP_CONF_AUTH_AND_ENC (REG_BIT(1) | REG_BIT(0))
#define PORT_HDCP_ANINIT(port) _PORT_HDCP_AUTHENC(port, 0x4)
#define _TRANSA_HDCP_ANINIT 0x66404
#define _TRANSB_HDCP_ANINIT 0x66504
Annotation
- Immediate include surface: `intel_display_reg_defs.h`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.