drivers/gpu/drm/i915/display/intel_lt_phy.c

File Facts

System

Linux kernel

Corpus path

drivers/gpu/drm/i915/display/intel_lt_phy.c

Extension

.c

Size

59613 bytes

Lines

2352

Domain

Driver Families

Bucket

drivers/gpu

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• drm/drm_print.h
• intel_cx0_phy.h
• intel_cx0_phy_regs.h
• intel_ddi.h
• intel_ddi_buf_trans.h
• intel_de.h
• intel_display.h
• intel_display_regs.h
• intel_display_types.h
• intel_display_utils.h
• intel_dpll.h
• intel_dpll_mgr.h
• intel_hdmi.h
• intel_lt_phy.h
• intel_lt_phy_regs.h
• intel_panel.h
• intel_psr.h
• intel_tc.h

Detected Declarations

• struct phy_param_t
• struct lt_phy_params
• struct intel_lt_phy_pll_params
• function intel_lt_phy_get_owned_lane_mask
• function intel_lt_phy_read
• function intel_lt_phy_write
• function intel_lt_phy_rmw
• function intel_lt_phy_clear_status_p2p
• function assert_dc_off
• function __intel_lt_phy_p2p_write_once
• function __intel_lt_phy_p2p_write
• function intel_lt_phy_p2p_write
• function intel_lt_phy_setup_powerdown
• function intel_lt_phy_powerdown_change_sequence
• function intel_lt_phy_lane_reset
• function intel_lt_phy_is_hdmi
• function intel_lt_phy_is_dp
• function intel_lt_phy_program_port_clock_ctl
• function intel_lt_phy_get_dp_clock
• function intel_lt_phy_config_changed
• function intel_lt_phy_transaction_end
• function intel_lt_phy_pll_tables_get
• function intel_lt_phy_pll_is_ssc_enabled
• function mul_q32_u32
• function calculate_target_dco_and_loop_cnt
• function set_phy_vdr_addresses
• function compute_ssc
• function compute_bias2
• function compute_tdc
• function compute_dco_med
• function compute_dco_fine
• function intel_lt_phy_calculate_hdmi_state
• function intel_lt_phy_calc_hdmi_port_clock
• function intel_lt_phy_calc_port_clock
• function intel_lt_phy_pll_calc_state
• function intel_lt_phy_tbt_pll_calc_state
• function intel_lt_phy_program_pll
• function intel_lt_phy_enable_disable_tx
• function intel_lt_phy_pll_enable
• function intel_lt_phy_pll_disable
• function intel_lt_phy_set_signal_levels
• function intel_lt_phy_dump_hw_state
• function intel_lt_phy_pll_compare_hw_state
• function intel_lt_phy_pll_is_enabled
• function intel_lt_phy_tbt_pll_readout_hw_state
• function intel_lt_phy_pll_readout_hw_state
• function intel_xe3plpd_pll_enable
• function intel_xe3plpd_pll_disable

Annotated Snippet

struct phy_param_t {
	u32 val;
	u32 addr;
};

struct lt_phy_params {
	struct phy_param_t pll_reg4;
	struct phy_param_t pll_reg3;
	struct phy_param_t pll_reg5;
	struct phy_param_t pll_reg57;
	struct phy_param_t lf;
	struct phy_param_t tdc;
	struct phy_param_t ssc;
	struct phy_param_t bias2;
	struct phy_param_t bias_trim;
	struct phy_param_t dco_med;
	struct phy_param_t dco_fine;
	struct phy_param_t ssc_inj;
	struct phy_param_t surv_bonus;
};

static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_rbr = {
	.config = {
		0x83,
		0x2d,
		0x0,
	},
	.addr_msb = {
		0x87,
		0x87,
		0x87,
		0x87,
		0x88,
		0x88,
		0x88,
		0x88,
		0x88,
		0x88,
		0x88,
		0x88,
		0x88,
	},
	.addr_lsb = {
		0x10,
		0x0c,
		0x14,
		0xe4,
		0x0c,
		0x10,
		0x14,
		0x18,
		0x48,
		0x40,
		0x4c,
		0x24,
		0x44,
	},
	.data = {
		{ 0x0,  0x4c, 0x2,  0x0  },
		{ 0x5,  0xa,  0x2a, 0x20 },
		{ 0x80, 0x0,  0x0,  0x0  },
		{ 0x4,  0x4,  0x82, 0x28 },
		{ 0xfa, 0x16, 0x83, 0x11 },
		{ 0x80, 0x0f, 0xf9, 0x53 },
		{ 0x84, 0x26, 0x5,  0x4  },
		{ 0x0,  0xe0, 0x1,  0x0  },
		{ 0x4b, 0x48, 0x0,  0x0  },
		{ 0x27, 0x8,  0x0,  0x0  },
		{ 0x5a, 0x13, 0x29, 0x13 },
		{ 0x0,  0x5b, 0xe0, 0x0a },
		{ 0x0,  0x0,  0x0,  0x0  },
	},
};

static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_hbr1 = {
	.config = {
		0x8b,
		0x2d,
		0x0,
	},
	.addr_msb = {
		0x87,
		0x87,
		0x87,
		0x87,
		0x88,
		0x88,
		0x88,
		0x88,
		0x88,

Annotation

• Immediate include surface: `drm/drm_print.h`, `intel_cx0_phy.h`, `intel_cx0_phy_regs.h`, `intel_ddi.h`, `intel_ddi_buf_trans.h`, `intel_de.h`, `intel_display.h`, `intel_display_regs.h`.
• Detected declarations: `struct phy_param_t`, `struct lt_phy_params`, `struct intel_lt_phy_pll_params`, `function intel_lt_phy_get_owned_lane_mask`, `function intel_lt_phy_read`, `function intel_lt_phy_write`, `function intel_lt_phy_rmw`, `function intel_lt_phy_clear_status_p2p`, `function assert_dc_off`, `function __intel_lt_phy_p2p_write_once`.
• Atlas domain: Driver Families / drivers/gpu.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.