drivers/gpu/drm/i915/display/intel_mchbar.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/i915/display/intel_mchbar.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/i915/display/intel_mchbar.c- Extension
.c- Size
- 1855 bytes
- Lines
- 79
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/minmax.hdrm/drm_print.hintel_de.hintel_display_core.hintel_mchbar.h
Detected Declarations
function has_mchbar_mirrorfunction mchbar_mirror_basefunction mchbar_mirror_endfunction mchbar_mirror_lenfunction is_mchbar_regfunction assert_is_mchbar_regfunction intel_mchbar_read16function intel_mchbar_readfunction intel_mchbar_read64_2x32
Annotated Snippet
// SPDX-License-Identifier: MIT
/*
* Copyright © 2026 Intel Corporation
*/
#include <linux/minmax.h>
#include <drm/drm_print.h>
#include "intel_de.h"
#include "intel_display_core.h"
#include "intel_mchbar.h"
static bool has_mchbar_mirror(struct intel_display *display)
{
return DISPLAY_VER(display) < 14;
}
static u32 mchbar_mirror_base(struct intel_display *display)
{
if (DISPLAY_VER(display) >= 6)
return MCHBAR_MIRROR_BASE_SNB;
else
return MCHBAR_MIRROR_BASE;
}
static u32 mchbar_mirror_end(struct intel_display *display)
{
if (DISPLAY_VER(display) >= 12 && !display->platform.rocketlake)
return MCHBAR_MIRROR_END_TGL;
else if (DISPLAY_VER(display) >= 11)
return MCHBAR_MIRROR_END_ICL_RKL;
else if (DISPLAY_VER(display) >= 6)
return MCHBAR_MIRROR_END_SNB;
else
return MCHBAR_MIRROR_END;
}
static u32 mchbar_mirror_len(struct intel_display *display)
{
return mchbar_mirror_end(display) - mchbar_mirror_base(display) + 1;
}
static bool is_mchbar_reg(struct intel_display *display, intel_reg_t reg)
{
return has_mchbar_mirror(display) &&
in_range32(intel_reg_offset(reg),
mchbar_mirror_base(display),
mchbar_mirror_len(display));
}
static void assert_is_mchbar_reg(struct intel_display *display, intel_reg_t reg)
{
drm_WARN(display->drm, !is_mchbar_reg(display, reg),
"Reading non-MCHBAR register 0x%x\n",
intel_reg_offset(reg));
}
u16 intel_mchbar_read16(struct intel_display *display, intel_reg_t reg)
{
assert_is_mchbar_reg(display, reg);
return intel_de_read16(display, reg);
}
u32 intel_mchbar_read(struct intel_display *display, intel_reg_t reg)
{
assert_is_mchbar_reg(display, reg);
return intel_de_read(display, reg);
}
u64 intel_mchbar_read64_2x32(struct intel_display *display, intel_reg_t reg)
{
assert_is_mchbar_reg(display, reg);
return intel_de_read64_2x32(display, reg);
}
Annotation
- Immediate include surface: `linux/minmax.h`, `drm/drm_print.h`, `intel_de.h`, `intel_display_core.h`, `intel_mchbar.h`.
- Detected declarations: `function has_mchbar_mirror`, `function mchbar_mirror_base`, `function mchbar_mirror_end`, `function mchbar_mirror_len`, `function is_mchbar_reg`, `function assert_is_mchbar_reg`, `function intel_mchbar_read16`, `function intel_mchbar_read`, `function intel_mchbar_read64_2x32`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.