drivers/gpu/drm/i915/display/intel_mg_phy_regs.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/i915/display/intel_mg_phy_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/i915/display/intel_mg_phy_regs.h
Extension
.h
Size
11927 bytes
Lines
283
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __INTEL_MG_PHY_REGS__
#define __INTEL_MG_PHY_REGS__

#include "intel_display_reg_defs.h"

#define MG_PHY_PORT_LN(ln, tc_port, ln0p1, ln0p2, ln1p1) \
	_MMIO(_PORT(tc_port, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))

#define MG_TX_LINK_PARAMS_TX1LN0_PORT1		0x16812C
#define MG_TX_LINK_PARAMS_TX1LN1_PORT1		0x16852C
#define MG_TX_LINK_PARAMS_TX1LN0_PORT2		0x16912C
#define MG_TX_LINK_PARAMS_TX1LN1_PORT2		0x16952C
#define MG_TX1_LINK_PARAMS(ln, tc_port) \
	MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
		       MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
		       MG_TX_LINK_PARAMS_TX1LN1_PORT1)

#define MG_TX_LINK_PARAMS_TX2LN0_PORT1		0x1680AC
#define MG_TX_LINK_PARAMS_TX2LN1_PORT1		0x1684AC
#define MG_TX_LINK_PARAMS_TX2LN0_PORT2		0x1690AC
#define MG_TX_LINK_PARAMS_TX2LN1_PORT2		0x1694AC
#define MG_TX2_LINK_PARAMS(ln, tc_port) \
	MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
		       MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
		       MG_TX_LINK_PARAMS_TX2LN1_PORT1)
#define   CRI_USE_FS32			(1 << 5)

#define MG_TX_PISO_READLOAD_TX1LN0_PORT1		0x16814C
#define MG_TX_PISO_READLOAD_TX1LN1_PORT1		0x16854C
#define MG_TX_PISO_READLOAD_TX1LN0_PORT2		0x16914C
#define MG_TX_PISO_READLOAD_TX1LN1_PORT2		0x16954C
#define MG_TX1_PISO_READLOAD(ln, tc_port) \
	MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
		       MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
		       MG_TX_PISO_READLOAD_TX1LN1_PORT1)

#define MG_TX_PISO_READLOAD_TX2LN0_PORT1		0x1680CC
#define MG_TX_PISO_READLOAD_TX2LN1_PORT1		0x1684CC
#define MG_TX_PISO_READLOAD_TX2LN0_PORT2		0x1690CC
#define MG_TX_PISO_READLOAD_TX2LN1_PORT2		0x1694CC
#define MG_TX2_PISO_READLOAD(ln, tc_port) \
	MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
		       MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
		       MG_TX_PISO_READLOAD_TX2LN1_PORT1)
#define   CRI_CALCINIT					(1 << 1)

#define MG_TX_SWINGCTRL_TX1LN0_PORT1		0x168148
#define MG_TX_SWINGCTRL_TX1LN1_PORT1		0x168548
#define MG_TX_SWINGCTRL_TX1LN0_PORT2		0x169148
#define MG_TX_SWINGCTRL_TX1LN1_PORT2		0x169548
#define MG_TX1_SWINGCTRL(ln, tc_port) \
	MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX1LN0_PORT1, \
		       MG_TX_SWINGCTRL_TX1LN0_PORT2, \
		       MG_TX_SWINGCTRL_TX1LN1_PORT1)

#define MG_TX_SWINGCTRL_TX2LN0_PORT1		0x1680C8
#define MG_TX_SWINGCTRL_TX2LN1_PORT1		0x1684C8
#define MG_TX_SWINGCTRL_TX2LN0_PORT2		0x1690C8
#define MG_TX_SWINGCTRL_TX2LN1_PORT2		0x1694C8
#define MG_TX2_SWINGCTRL(ln, tc_port) \
	MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX2LN0_PORT1, \
		       MG_TX_SWINGCTRL_TX2LN0_PORT2, \
		       MG_TX_SWINGCTRL_TX2LN1_PORT1)
#define   CRI_TXDEEMPH_OVERRIDE_17_12(x)		((x) << 0)
#define   CRI_TXDEEMPH_OVERRIDE_17_12_MASK		(0x3F << 0)

#define MG_TX_DRVCTRL_TX1LN0_TXPORT1			0x168144
#define MG_TX_DRVCTRL_TX1LN1_TXPORT1			0x168544
#define MG_TX_DRVCTRL_TX1LN0_TXPORT2			0x169144
#define MG_TX_DRVCTRL_TX1LN1_TXPORT2			0x169544
#define MG_TX_DRVCTRL_TX1LN0_TXPORT3			0x16A144
#define MG_TX_DRVCTRL_TX1LN1_TXPORT3			0x16A544
#define MG_TX_DRVCTRL_TX1LN0_TXPORT4			0x16B144
#define MG_TX_DRVCTRL_TX1LN1_TXPORT4			0x16B544
#define MG_TX1_DRVCTRL(ln, tc_port) \
	MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \
		       MG_TX_DRVCTRL_TX1LN0_TXPORT2, \
		       MG_TX_DRVCTRL_TX1LN1_TXPORT1)

#define MG_TX_DRVCTRL_TX2LN0_PORT1			0x1680C4
#define MG_TX_DRVCTRL_TX2LN1_PORT1			0x1684C4
#define MG_TX_DRVCTRL_TX2LN0_PORT2			0x1690C4
#define MG_TX_DRVCTRL_TX2LN1_PORT2			0x1694C4
#define MG_TX2_DRVCTRL(ln, tc_port) \
	MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX2LN0_PORT1, \
		       MG_TX_DRVCTRL_TX2LN0_PORT2, \
		       MG_TX_DRVCTRL_TX2LN1_PORT1)
#define   CRI_TXDEEMPH_OVERRIDE_11_6(x)			((x) << 24)
#define   CRI_TXDEEMPH_OVERRIDE_11_6_MASK		(0x3F << 24)
#define   CRI_TXDEEMPH_OVERRIDE_EN			(1 << 22)

Annotation

Implementation Notes