drivers/gpu/drm/i915/display/intel_sprite_regs.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/i915/display/intel_sprite_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/i915/display/intel_sprite_regs.h
Extension
.h
Size
18075 bytes
Lines
389
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __INTEL_SPRITE_REGS__
#define __INTEL_SPRITE_REGS__

#include "intel_display_reg_defs.h"

/* g4x/ilk/snb video sprite */
#define _DVSACNTR		0x72180
#define _DVSBCNTR		0x73180
#define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR)
#define   DVS_ENABLE			REG_BIT(31)
#define   DVS_PIPE_GAMMA_ENABLE		REG_BIT(30)
#define   DVS_YUV_RANGE_CORRECTION_DISABLE	REG_BIT(27)
#define   DVS_FORMAT_MASK		REG_GENMASK(26, 25)
#define   DVS_FORMAT_YUV422		REG_FIELD_PREP(DVS_FORMAT_MASK, 0)
#define   DVS_FORMAT_RGBX101010		REG_FIELD_PREP(DVS_FORMAT_MASK, 1)
#define   DVS_FORMAT_RGBX888		REG_FIELD_PREP(DVS_FORMAT_MASK, 2)
#define   DVS_FORMAT_RGBX161616		REG_FIELD_PREP(DVS_FORMAT_MASK, 3)
#define   DVS_PIPE_CSC_ENABLE		REG_BIT(24)
#define   DVS_SOURCE_KEY		REG_BIT(22)
#define   DVS_RGB_ORDER_XBGR		REG_BIT(20)
#define   DVS_YUV_FORMAT_BT709		REG_BIT(18)
#define   DVS_YUV_ORDER_MASK		REG_GENMASK(17, 16)
#define   DVS_YUV_ORDER_YUYV		REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 0)
#define   DVS_YUV_ORDER_UYVY		REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 1)
#define   DVS_YUV_ORDER_YVYU		REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 2)
#define   DVS_YUV_ORDER_VYUY		REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 3)
#define   DVS_ROTATE_180		REG_BIT(15)
#define   DVS_TRICKLE_FEED_DISABLE	REG_BIT(14)
#define   DVS_TILED			REG_BIT(10)
#define   DVS_DEST_KEY			REG_BIT(2)

#define _DVSALINOFF		0x72184
#define _DVSBLINOFF		0x73184
#define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)

#define _DVSASTRIDE		0x72188
#define _DVSBSTRIDE		0x73188
#define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)

#define _DVSAPOS		0x7218c
#define _DVSBPOS		0x7318c
#define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS)
#define   DVS_POS_Y_MASK		REG_GENMASK(31, 16)
#define   DVS_POS_Y(y)			REG_FIELD_PREP(DVS_POS_Y_MASK, (y))
#define   DVS_POS_X_MASK		REG_GENMASK(15, 0)
#define   DVS_POS_X(x)			REG_FIELD_PREP(DVS_POS_X_MASK, (x))

#define _DVSASIZE		0x72190
#define _DVSBSIZE		0x73190
#define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE)
#define   DVS_HEIGHT_MASK		REG_GENMASK(31, 16)
#define   DVS_HEIGHT(h)			REG_FIELD_PREP(DVS_HEIGHT_MASK, (h))
#define   DVS_WIDTH_MASK		REG_GENMASK(15, 0)
#define   DVS_WIDTH(w)			REG_FIELD_PREP(DVS_WIDTH_MASK, (w))

#define _DVSAKEYVAL		0x72194
#define _DVSBKEYVAL		0x73194
#define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)

#define _DVSAKEYMSK		0x72198
#define _DVSBKEYMSK		0x73198
#define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)

#define _DVSASURF		0x7219c
#define _DVSBSURF		0x7319c
#define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF)
#define   DVS_ADDR_MASK			REG_GENMASK(31, 12)

#define _DVSAKEYMAXVAL		0x721a0
#define _DVSBKEYMAXVAL		0x731a0
#define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)

#define _DVSATILEOFF		0x721a4
#define _DVSBTILEOFF		0x731a4
#define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
#define   DVS_OFFSET_Y_MASK		REG_GENMASK(31, 16)
#define   DVS_OFFSET_Y(y)		REG_FIELD_PREP(DVS_OFFSET_Y_MASK, (y))
#define   DVS_OFFSET_X_MASK		REG_GENMASK(15, 0)
#define   DVS_OFFSET_X(x)		REG_FIELD_PREP(DVS_OFFSET_X_MASK, (x))

#define _DVSASURFLIVE		0x721ac
#define _DVSBSURFLIVE		0x731ac
#define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)

#define _DVSAGAMC_G4X		0x721e0 /* g4x */
#define _DVSBGAMC_G4X		0x731e0 /* g4x */
#define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */

#define _DVSASCALE		0x72204
#define _DVSBSCALE		0x73204

Annotation

Implementation Notes