drivers/gpu/drm/i915/display/intel_vrr.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/i915/display/intel_vrr.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/i915/display/intel_vrr.c
Extension
.c
Size
39971 bytes
Lines
1229
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (trans_vrr_ctl & VRR_CTL_PIPELINE_FULL_OVERRIDE) {
			crtc_state->vrr.pipeline_full =
				REG_FIELD_GET(VRR_CTL_PIPELINE_FULL_MASK, trans_vrr_ctl);

			crtc_state->vrr.guardband =
				intel_vrr_pipeline_full_to_guardband(crtc_state,
								     crtc_state->vrr.pipeline_full);
		}
	}

	if (trans_vrr_ctl & VRR_CTL_FLIP_LINE_EN) {
		crtc_state->vrr.flipline = intel_de_read(display,
							 TRANS_VRR_FLIPLINE(display, cpu_transcoder)) + 1;
		crtc_state->vrr.vmax = intel_de_read(display,
						     TRANS_VRR_VMAX(display, cpu_transcoder)) + 1;
		crtc_state->vrr.vmin = intel_de_read(display,
						     TRANS_VRR_VMIN(display, cpu_transcoder)) + 1;

		if (DISPLAY_VER(display) < 13) {
			/* undo what intel_vrr_hw_value() does when writing the values */
			crtc_state->vrr.flipline += crtc_state->set_context_latency;
			crtc_state->vrr.vmax += crtc_state->set_context_latency;
			crtc_state->vrr.vmin += crtc_state->set_context_latency;

			crtc_state->vrr.vmin += intel_vrr_vmin_flipline_offset(display);
		}

		/*
		 * For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal
		 * bits are not filled. Since for these platforms TRAN_VMIN is always
		 * filled with crtc_vtotal, use TRAN_VRR_VMIN to get the vtotal for
		 * adjusted_mode.
		 */
		if (intel_vrr_always_use_vrr_tg(display))
			crtc_state->hw.adjusted_mode.crtc_vtotal =
				intel_vrr_vmin_vtotal(crtc_state);

		if (HAS_AS_SDP(display)) {
			trans_vrr_vsync =
				intel_de_read(display,
					      TRANS_VRR_VSYNC(display, cpu_transcoder));
			crtc_state->vrr.vsync_start =
				REG_FIELD_GET(VRR_VSYNC_START_MASK, trans_vrr_vsync);
			crtc_state->vrr.vsync_end =
				REG_FIELD_GET(VRR_VSYNC_END_MASK, trans_vrr_vsync);
		}
	}

	vrr_enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE;

	if (intel_vrr_always_use_vrr_tg(display))
		crtc_state->vrr.enable = vrr_enable && !intel_vrr_is_fixed_rr(crtc_state);
	else
		crtc_state->vrr.enable = vrr_enable;

	intel_vrr_get_dc_balance_config(crtc_state);

	/*
	 * #TODO: For Both VRR and CMRR the flag I915_MODE_FLAG_VRR is set for mode_flags.
	 * Since CMRR is currently disabled, set this flag for VRR for now.
	 * Need to keep this in mind while re-enabling CMRR.
	 */
	if (crtc_state->vrr.enable)
		crtc_state->mode_flags |= I915_MODE_FLAG_VRR;

	/*
	 * For platforms that always use the VRR timing generator, we overwrite
	 * crtc_vblank_start with vtotal - guardband to reflect the delayed
	 * vblank start. This works for both default and optimized guardband values.
	 * On other platforms, we keep the original value from
	 * intel_get_transcoder_timings() and apply adjustments only in VRR-specific
	 * paths as needed.
	 */
	if (intel_vrr_always_use_vrr_tg(display))
		crtc_state->hw.adjusted_mode.crtc_vblank_start =
			crtc_state->hw.adjusted_mode.crtc_vtotal -
			crtc_state->vrr.guardband;
}

int intel_vrr_safe_window_start(const struct intel_crtc_state *crtc_state)
{
	struct intel_display *display = to_intel_display(crtc_state);

	if (DISPLAY_VER(display) >= 30)
		return crtc_state->hw.adjusted_mode.crtc_vdisplay -
		       crtc_state->set_context_latency;
	else
		return crtc_state->hw.adjusted_mode.crtc_vdisplay;
}

Annotation

Implementation Notes