drivers/gpu/drm/i915/display/intel_vrr_regs.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/i915/display/intel_vrr_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/i915/display/intel_vrr_regs.h
Extension
.h
Size
8801 bytes
Lines
196
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __INTEL_VRR_REGS_H__
#define __INTEL_VRR_REGS_H__

#include "intel_display_reg_defs.h"

#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_A	0x604d4
#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_B	0x614d4
#define TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(trans)	_MMIO_TRANS(trans, \
							    _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_A, \
							    _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_B)
#define  VRR_DCB_ADJ_FLIPLINE_CNT_MASK		REG_GENMASK(31, 24)
#define  VRR_DCB_ADJ_FLIPLINE_MASK		REG_GENMASK(19, 0)
#define  VRR_DCB_ADJ_FLIPLINE(flipline)		REG_FIELD_PREP(VRR_DCB_ADJ_FLIPLINE_MASK, \
							       (flipline))

#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE_A		0x90700
#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE_B		0x98700
#define TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE(trans)	_MMIO_TRANS(trans, \
								    _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE_A, \
								    _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE_B)

#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_A		0x604d8
#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_B		0x614d8
#define TRANS_VRR_DCB_ADJ_VMAX_CFG(trans)	_MMIO_TRANS(trans, \
							    _TRANS_VRR_DCB_ADJ_VMAX_CFG_A, \
							    _TRANS_VRR_DCB_ADJ_VMAX_CFG_B)
#define  VRR_DCB_ADJ_VMAX_CNT_MASK		REG_GENMASK(31, 24)
#define  VRR_DCB_ADJ_VMAX_MASK			REG_GENMASK(19, 0)
#define  VRR_DCB_ADJ_VMAX(vmax)			REG_FIELD_PREP(VRR_DCB_ADJ_VMAX_MASK, (vmax))

#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE_A	0x906f8
#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE_B	0x986f8
#define TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE(trans)	_MMIO_TRANS(trans, \
							    _TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE_A, \
							    _TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE_B)

#define _TRANS_VRR_DCB_FLIPLINE_A		0x60418
#define _TRANS_VRR_DCB_FLIPLINE_B		0x61418
#define TRANS_VRR_DCB_FLIPLINE(trans)		_MMIO_TRANS(trans, \
							    _TRANS_VRR_DCB_FLIPLINE_A, \
							    _TRANS_VRR_DCB_FLIPLINE_B)
#define  VRR_DCB_FLIPLINE_MASK			REG_GENMASK(19, 0)
#define  VRR_DCB_FLIPLINE(flipline)		REG_FIELD_PREP(VRR_DCB_FLIPLINE_MASK, \
							       (flipline))

#define _TRANS_VRR_DCB_FLIPLINE_LIVE_A		0x906fc
#define _TRANS_VRR_DCB_FLIPLINE_LIVE_B		0x986fc
#define TRANS_VRR_DCB_FLIPLINE_LIVE(trans)	_MMIO_TRANS(trans, \
							    _TRANS_VRR_DCB_FLIPLINE_LIVE_A, \
							    _TRANS_VRR_DCB_FLIPLINE_LIVE_B)

#define _TRANS_VRR_DCB_VMAX_A			0x60414
#define _TRANS_VRR_DCB_VMAX_B			0x61414
#define TRANS_VRR_DCB_VMAX(trans)		_MMIO_TRANS(trans, \
							     _TRANS_VRR_DCB_VMAX_A, \
							     _TRANS_VRR_DCB_VMAX_B)
#define  VRR_DCB_VMAX_MASK			REG_GENMASK(19, 0)
#define  VRR_DCB_VMAX(vmax)			REG_FIELD_PREP(VRR_DCB_VMAX_MASK, (vmax))

#define _TRANS_VRR_DCB_VMAX_LIVE_A		0x906f4
#define _TRANS_VRR_DCB_VMAX_LIVE_B		0x986f4
#define TRANS_VRR_DCB_VMAX_LIVE(trans)		_MMIO_TRANS(trans, \
							    _TRANS_VRR_DCB_VMAX_LIVE_A, \
							    _TRANS_VRR_DCB_VMAX_LIVE_B)

#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_A		0x604c0
#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_B		0x614c0
#define TRANS_ADAPTIVE_SYNC_DCB_CTL(trans)	_MMIO_TRANS(trans, \
							     _TRANS_ADAPTIVE_SYNC_DCB_CTL_A, \
							     _TRANS_ADAPTIVE_SYNC_DCB_CTL_B)
#define  ADAPTIVE_SYNC_COUNTER_EN		REG_BIT(31)

#define _TRANS_VRR_CTL_A			0x60420
#define _TRANS_VRR_CTL_B			0x61420
#define _TRANS_VRR_CTL_C			0x62420
#define _TRANS_VRR_CTL_D			0x63420
#define TRANS_VRR_CTL(display, trans)		_MMIO_TRANS2((display), (trans), _TRANS_VRR_CTL_A)
#define   VRR_CTL_VRR_ENABLE			REG_BIT(31)
#define   VRR_CTL_IGN_MAX_SHIFT			REG_BIT(30)
#define   VRR_CTL_FLIP_LINE_EN			REG_BIT(29)
#define   VRR_CTL_CMRR_ENABLE			REG_BIT(27)
#define   VRR_CTL_PIPELINE_FULL_MASK		REG_GENMASK(10, 3)
#define   VRR_CTL_PIPELINE_FULL(x)		REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))
#define   VRR_CTL_DCB_ADJ_ENABLE		REG_BIT(28)
#define   VRR_CTL_PIPELINE_FULL_OVERRIDE	REG_BIT(0)
#define   XELPD_VRR_CTL_VRR_GUARDBAND_MASK	REG_GENMASK(15, 0)
#define   XELPD_VRR_CTL_VRR_GUARDBAND(x)	REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x))

#define _TRANS_VRR_VMAX_A			0x60424
#define _TRANS_VRR_VMAX_B			0x61424

Annotation

Implementation Notes