drivers/gpu/drm/i915/display/skl_universal_plane.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/i915/display/skl_universal_plane.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/i915/display/skl_universal_plane.c- Extension
.c- Size
- 93915 bytes
- Lines
- 3253
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
drm/drm_atomic_helper.hdrm/drm_blend.hdrm/drm_damage_helper.hdrm/drm_fourcc.hdrm/drm_print.hdrm/intel/step.hintel_bo.hintel_color.hintel_color_pipeline.hintel_de.hintel_display_irq.hintel_display_regs.hintel_display_types.hintel_display_utils.hintel_display_wa.hintel_fb.hintel_fbc.hintel_frontbuffer.hintel_parent.hintel_plane.hintel_psr.hintel_psr_regs.hskl_scaler.hskl_universal_plane.hskl_universal_plane_regs.hskl_watermark.h
Detected Declarations
function skl_format_to_fourccfunction icl_nv12_y_plane_maskfunction icl_is_nv12_y_planefunction icl_hdr_plane_maskfunction icl_is_hdr_planefunction icl_plane_min_cdclkfunction glk_plane_ratiofunction glk_plane_min_cdclkfunction skl_plane_ratiofunction skl_plane_min_cdclkfunction skl_plane_max_widthfunction glk_plane_max_widthfunction adl_plane_min_widthfunction icl_plane_min_widthfunction xe3_plane_max_widthfunction icl_hdr_plane_max_widthfunction icl_sdr_plane_max_widthfunction skl_plane_max_heightfunction skl_fbc_id_for_pipefunction skl_plane_has_fbcfunction icl_plane_max_heightfunction plane_max_stridefunction adl_plane_max_stridefunction skl_plane_max_stridefunction tgl_plane_can_async_flipfunction icl_plane_can_async_flipfunction skl_plane_can_async_flipfunction tgl_plane_min_alignmentfunction skl_plane_min_alignmentfunction icl_program_input_cscfunction skl_plane_stride_multfunction skl_plane_stridefunction skl_plane_ddb_reg_valfunction xe3_plane_min_ddb_reg_valfunction skl_plane_wm_reg_valfunction skl_write_plane_wmfunction skl_plane_disable_armfunction icl_plane_disable_sel_fetch_armfunction plane_has_normalizerfunction pixel_normalizer_valuefunction icl_plane_disable_armfunction skl_plane_get_hw_statefunction skl_plane_ctl_formatfunction skl_plane_ctl_alphafunction glk_plane_color_ctl_alphafunction skl_plane_ctl_tilingfunction skl_plane_ctl_rotatefunction icl_plane_ctl_flip
Annotated Snippet
if (rgb_order) {
if (alpha)
return DRM_FORMAT_ABGR8888;
else
return DRM_FORMAT_XBGR8888;
} else {
if (alpha)
return DRM_FORMAT_ARGB8888;
else
return DRM_FORMAT_XRGB8888;
}
case PLANE_CTL_FORMAT_XRGB_2101010:
if (rgb_order) {
if (alpha)
return DRM_FORMAT_ABGR2101010;
else
return DRM_FORMAT_XBGR2101010;
} else {
if (alpha)
return DRM_FORMAT_ARGB2101010;
else
return DRM_FORMAT_XRGB2101010;
}
case PLANE_CTL_FORMAT_XRGB_16161616F:
if (rgb_order) {
if (alpha)
return DRM_FORMAT_ABGR16161616F;
else
return DRM_FORMAT_XBGR16161616F;
} else {
if (alpha)
return DRM_FORMAT_ARGB16161616F;
else
return DRM_FORMAT_XRGB16161616F;
}
}
}
static u8 icl_nv12_y_plane_mask(struct intel_display *display)
{
if (DISPLAY_VER(display) >= 13 || HAS_D12_PLANE_MINIMIZATION(display))
return BIT(PLANE_4) | BIT(PLANE_5);
else
return BIT(PLANE_6) | BIT(PLANE_7);
}
bool icl_is_nv12_y_plane(struct intel_display *display,
enum plane_id plane_id)
{
return DISPLAY_VER(display) >= 11 &&
icl_nv12_y_plane_mask(display) & BIT(plane_id);
}
u8 icl_hdr_plane_mask(void)
{
return BIT(PLANE_1) | BIT(PLANE_2) | BIT(PLANE_3);
}
bool icl_is_hdr_plane(struct intel_display *display, enum plane_id plane_id)
{
return DISPLAY_VER(display) >= 11 &&
icl_hdr_plane_mask() & BIT(plane_id);
}
static int icl_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state);
/* two pixels per clock */
return DIV_ROUND_UP(pixel_rate, 2);
}
static void
glk_plane_ratio(const struct intel_plane_state *plane_state,
unsigned int *num, unsigned int *den)
{
const struct drm_framebuffer *fb = plane_state->hw.fb;
if (fb->format->cpp[0] == 8) {
*num = 10;
*den = 8;
} else {
*num = 1;
*den = 1;
}
}
static int glk_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
Annotation
- Immediate include surface: `drm/drm_atomic_helper.h`, `drm/drm_blend.h`, `drm/drm_damage_helper.h`, `drm/drm_fourcc.h`, `drm/drm_print.h`, `drm/intel/step.h`, `intel_bo.h`, `intel_color.h`.
- Detected declarations: `function skl_format_to_fourcc`, `function icl_nv12_y_plane_mask`, `function icl_is_nv12_y_plane`, `function icl_hdr_plane_mask`, `function icl_is_hdr_plane`, `function icl_plane_min_cdclk`, `function glk_plane_ratio`, `function glk_plane_min_cdclk`, `function skl_plane_ratio`, `function skl_plane_min_cdclk`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.