drivers/gpu/drm/i915/display/skl_watermark.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/i915/display/skl_watermark.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/i915/display/skl_watermark.c- Extension
.c- Size
- 115717 bytes
- Lines
- 4095
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: operation-table or driver-model contract
- Status
- pattern implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines an operation table; this is where Linux turns generic core objects into subsystem-specific behavior.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/debugfs.hdrm/drm_blend.hdrm/drm_print.hdrm/intel/intel_pcode_regs.hi9xx_wm.hintel_atomic.hintel_bw.hintel_cdclk.hintel_crtc.hintel_cursor_regs.hintel_de.hintel_display.hintel_display_power.hintel_display_regs.hintel_display_rpm.hintel_display_types.hintel_display_utils.hintel_display_wa.hintel_dram.hintel_fb.hintel_fixed.hintel_flipq.hintel_parent.hintel_plane.hintel_vblank.hintel_wm.hskl_prefill.hskl_scaler.hskl_universal_plane_regs.hskl_watermark.hskl_watermark_regs.h
Detected Declarations
struct intel_dbuf_statestruct skl_wm_paramsstruct dbuf_slice_conf_entrystruct skl_plane_ddb_iterstruct skl_hw_statefunction intel_enabled_dbuf_slices_maskfunction for_each_dbuf_slicefunction skl_needs_memory_bw_wafunction intel_has_sagvfunction intel_sagv_block_timefunction intel_sagv_initfunction skl_sagv_enablefunction skl_sagv_disablefunction skl_sagv_pre_plane_updatefunction skl_sagv_post_plane_updatefunction intel_sagv_pre_plane_updatefunction intel_sagv_post_plane_updatefunction skl_crtc_can_enable_sagvfunction for_each_plane_id_on_crtcfunction for_each_plane_id_on_crtcfunction tgl_crtc_can_enable_sagvfunction for_each_plane_id_on_crtcfunction intel_crtc_can_enable_sagvfunction skl_ddb_entry_initfunction intel_dbuf_slice_sizefunction skl_ddb_entry_for_slicesfunction mbus_ddb_offsetfunction skl_ddb_dbuf_slice_maskfunction intel_crtc_ddb_weightfunction intel_crtc_dbuf_weightsfunction for_each_pipefunction skl_crtc_allocate_ddbfunction skl_wm_latencyfunction skl_cursor_allocationfunction skl_ddb_entry_init_from_hwfunction skl_ddb_get_hw_plane_statefunction skl_pipe_ddb_get_hw_statefunction check_mbus_joinedfunction adlp_check_mbus_joinedfunction compute_dbuf_slicesfunction icl_compute_dbuf_slicesfunction tgl_compute_dbuf_slicesfunction adlp_compute_dbuf_slicesfunction dg2_compute_dbuf_slicesfunction skl_compute_dbuf_slicesfunction use_minimal_wm0_onlyfunction skl_plane_relative_data_ratefunction skl_total_relative_data_rate
Annotated Snippet
static const struct file_operations skl_watermark_ipc_status_fops = {
.owner = THIS_MODULE,
.open = skl_watermark_ipc_status_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
.write = skl_watermark_ipc_status_write
};
static int intel_sagv_status_show(struct seq_file *m, void *unused)
{
struct intel_display *display = m->private;
static const char * const sagv_status[] = {
[I915_SAGV_UNKNOWN] = "unknown",
[I915_SAGV_DISABLED] = "disabled",
[I915_SAGV_ENABLED] = "enabled",
[I915_SAGV_NOT_CONTROLLED] = "not controlled",
};
seq_printf(m, "SAGV available: %s\n", str_yes_no(intel_has_sagv(display)));
seq_printf(m, "SAGV modparam: %s\n",
str_enabled_disabled(display->params.enable_sagv));
seq_printf(m, "SAGV status: %s\n", sagv_status[display->sagv.status]);
seq_printf(m, "SAGV block time: %d usec\n", display->sagv.block_time_us);
return 0;
}
DEFINE_SHOW_ATTRIBUTE(intel_sagv_status);
void skl_watermark_debugfs_register(struct intel_display *display)
{
struct dentry *debugfs_root = display->drm->debugfs_root;
if (HAS_IPC(display))
debugfs_create_file("i915_ipc_status", 0644, debugfs_root,
display, &skl_watermark_ipc_status_fops);
if (HAS_SAGV(display))
debugfs_create_file("i915_sagv_status", 0444, debugfs_root,
display, &intel_sagv_status_fops);
}
unsigned int skl_watermark_max_latency(struct intel_display *display, int initial_wm_level)
{
int level;
for (level = display->wm.num_levels - 1; level >= initial_wm_level; level--) {
unsigned int latency = skl_wm_latency(display, level, NULL);
if (latency)
return latency;
}
return 0;
}
Annotation
- Immediate include surface: `linux/debugfs.h`, `drm/drm_blend.h`, `drm/drm_print.h`, `drm/intel/intel_pcode_regs.h`, `i9xx_wm.h`, `intel_atomic.h`, `intel_bw.h`, `intel_cdclk.h`.
- Detected declarations: `struct intel_dbuf_state`, `struct skl_wm_params`, `struct dbuf_slice_conf_entry`, `struct skl_plane_ddb_iter`, `struct skl_hw_state`, `function intel_enabled_dbuf_slices_mask`, `function for_each_dbuf_slice`, `function skl_needs_memory_bw_wa`, `function intel_has_sagv`, `function intel_sagv_block_time`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: pattern implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.