drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
Extension
.h
Size
14584 bytes
Lines
310
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __VLV_DPIO_PHY_REGS_H__
#define __VLV_DPIO_PHY_REGS_H__

#include "intel_display_reg_defs.h"

#define _VLV_CMN(dw) (0x8100 + (dw) * 4)
#define _CHV_CMN(cl, dw) (0x8100 - (cl) * 0x80 + (dw) * 4)
#define _VLV_PLL(ch, dw) (0x8000 + (ch) * 0x20 + (dw) * 4) /* dw 0-7,16-23 */
#define _CHV_PLL(ch, dw) (0x8000 + (ch) * 0x180 + (dw) * 4)
#define _VLV_REF(dw) (0x80a0 + ((dw) - 8) * 4) /* dw 8-15 */
#define _VLV_PCS(ch, spline, dw) (0x200 + (ch) * 0x2400 + (spline) * 0x200 + (dw) * 4)
#define _VLV_PCS_GRP(ch, dw) (0x8200 + (ch) * 0x200 + (dw) * 4)
#define _VLV_PCS_BCAST(dw) (0xc000 + (dw) * 4)
#define _VLV_TX(ch, lane, dw) (0x80 + (ch) * 0x2400 + (lane) * 0x200 + (dw) * 4)
#define _VLV_TX_GRP(ch, dw) (0x8280 + (ch) * 0x200 + (dw) * 4)
#define _VLV_TX_BCAST(dw) (0xc080 + (dw) * 4)

/*
 * Per pipe/PLL DPIO regs
 */
#define VLV_PLL_DW3(ch)			_VLV_PLL((ch), 3)
#define   DPIO_S1_DIV_MASK		REG_GENMASK(30, 28)
#define   DPIO_S1_DIV(s1)		REG_FIELD_PREP(DPIO_S1_DIV_MASK, (s1))
#define   DPIO_S1_DIV_DAC		0 /* 10, DAC 25-225M rate */
#define   DPIO_S1_DIV_HDMIDP		1 /* 5, DAC 225-400M rate */
#define   DPIO_S1_DIV_LVDS1		2 /* 14 */
#define   DPIO_S1_DIV_LVDS2		3 /* 7 */
#define   DPIO_K_DIV_MASK		REG_GENMASK(27, 24)
#define   DPIO_K_DIV(k)			REG_FIELD_PREP(DPIO_K_DIV_MASK, (k))
#define   DPIO_P1_DIV_MASK		REG_GENMASK(23, 21)
#define   DPIO_P1_DIV(p1)		REG_FIELD_PREP(DPIO_P1_DIV_MASK, (p1))
#define   DPIO_P2_DIV_MASK		REG_GENMASK(20, 16)
#define   DPIO_P2_DIV(p2)		REG_FIELD_PREP(DPIO_P2_DIV_MASK, (p2))
#define   DPIO_N_DIV_MASK		REG_GENMASK(15, 12)
#define   DPIO_N_DIV(n)			REG_FIELD_PREP(DPIO_N_DIV_MASK, (n))
#define   DPIO_ENABLE_CALIBRATION	REG_BIT(11)
#define   DPIO_M1_DIV_MASK		REG_GENMASK(10, 8)
#define   DPIO_M1_DIV(m1)		REG_FIELD_PREP(DPIO_M1_DIV_MASK, (m1))
#define   DPIO_M2_DIV_MASK		REG_GENMASK(7, 0)
#define   DPIO_M2_DIV(m2)		REG_FIELD_PREP(DPIO_M2_DIV_MASK, (m2))

#define VLV_PLL_DW5(ch)			_VLV_PLL((ch), 5)
#define   DPIO_REFSEL_OVERRIDE		REG_BIT(27)
#define   DPIO_PLL_MODESEL_MASK		REG_GENMASK(26, 24)
#define   DPIO_BIAS_CURRENT_CTL_MASK	REG_GENMASK(22, 20) /* always 0x7 */
#define   DPIO_PLL_REFCLK_SEL_MASK	REG_GENMASK(17, 16)
#define   DPIO_DRIVER_CTL_MASK		REG_GENMASK(15, 12) /* always set to 0x8 */
#define   DPIO_CLK_BIAS_CTL_MASK	REG_GENMASK(11, 8) /* always set to 0x5 */

#define VLV_PLL_DW7(ch)			_VLV_PLL((ch), 7)

#define VLV_PLL_DW16(ch)		_VLV_PLL((ch), 16)

#define VLV_PLL_DW17(ch)		_VLV_PLL((ch), 17)

#define VLV_PLL_DW18(ch)		_VLV_PLL((ch), 18)

#define VLV_PLL_DW19(ch)		_VLV_PLL((ch), 19)

#define VLV_REF_DW11			_VLV_REF(11)

#define VLV_CMN_DW0			_VLV_CMN(0)

/*
 * Per DDI channel DPIO regs
 */
#define VLV_PCS_DW0_GRP(ch)		_VLV_PCS_GRP((ch), 0)
#define VLV_PCS01_DW0(ch)		_VLV_PCS((ch), 0, 0)
#define VLV_PCS23_DW0(ch)		_VLV_PCS((ch), 1, 0)
#define   DPIO_PCS_TX_LANE2_RESET	REG_BIT(16)
#define   DPIO_PCS_TX_LANE1_RESET	REG_BIT(7)
#define   DPIO_LEFT_TXFIFO_RST_MASTER2	REG_BIT(4)
#define   DPIO_RIGHT_TXFIFO_RST_MASTER2	REG_BIT(3)

#define VLV_PCS_DW1_GRP(ch)		 _VLV_PCS_GRP((ch), 1)
#define VLV_PCS01_DW1(ch) _VLV_PCS((ch), 0, 1)
#define VLV_PCS23_DW1(ch) _VLV_PCS((ch), 1, 1)
#define   CHV_PCS_REQ_SOFTRESET_EN		REG_BIT(23)
#define   DPIO_PCS_CLK_CRI_RXEB_EIOS_EN		REG_BIT(22)
#define   DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN	REG_BIT(21)
#define   DPIO_PCS_CLK_DATAWIDTH_MASK		REG_GENMASK(7, 6)
#define   DPIO_PCS_CLK_DATAWIDTH_8_10		REG_FIELD_PREP(DPIO_PCS_CLK_DATAWIDTH_MASK, 1)
#define   DPIO_PCS_CLK_DATAWIDTH_16_20		REG_FIELD_PREP(DPIO_PCS_CLK_DATAWIDTH_MASK, 2)
#define   DPIO_PCS_CLK_DATAWIDTH_32_40		REG_FIELD_PREP(DPIO_PCS_CLK_DATAWIDTH_MASK, 3)
#define   DPIO_PCS_CLK_SOFT_RESET		REG_BIT(5)

#define VLV_PCS_DW8_GRP(ch)		_VLV_PCS_GRP((ch), 8)
#define VLV_PCS01_DW8(ch)		_VLV_PCS((ch), 0, 8)
#define VLV_PCS23_DW8(ch)		_VLV_PCS((ch), 1, 8)
#define   DPIO_PCS_USEDCLKCHANNEL		REG_BIT(21)

Annotation

Implementation Notes