drivers/gpu/drm/i915/display/vlv_dsi.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/i915/display/vlv_dsi.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/i915/display/vlv_dsi.c
Extension
.c
Size
65869 bytes
Lines
2058
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (!(intel_de_read(display, MIPI_DEVICE_READY(display, port)) & DEVICE_READY)) {
			intel_de_rmw(display, MIPI_DEVICE_READY(display, port),
				     ULPS_STATE_MASK, DEVICE_READY);
			usleep_range(10, 15);
		} else {
			/* Enter ULPS */
			intel_de_rmw(display, MIPI_DEVICE_READY(display, port),
				     ULPS_STATE_MASK, ULPS_STATE_ENTER | DEVICE_READY);

			/* Wait for ULPS active */
			if (intel_de_wait_for_clear_ms(display, MIPI_CTRL(display, port),
						       GLK_ULPS_NOT_ACTIVE, 20))
				drm_err(display->drm, "ULPS not active\n");

			/* Exit ULPS */
			intel_de_rmw(display, MIPI_DEVICE_READY(display, port),
				     ULPS_STATE_MASK, ULPS_STATE_EXIT | DEVICE_READY);

			/* Enter Normal Mode */
			intel_de_rmw(display, MIPI_DEVICE_READY(display, port),
				     ULPS_STATE_MASK,
				     ULPS_STATE_NORMAL_OPERATION | DEVICE_READY);

			intel_de_rmw(display, MIPI_CTRL(display, port), GLK_LP_WAKE, 0);
		}
	}

	/* Wait for Stop state */
	for_each_dsi_port(port, intel_dsi->ports) {
		if (intel_de_wait_for_set_ms(display, MIPI_CTRL(display, port),
					     GLK_DATA_LANE_STOP_STATE, 20))
			drm_err(display->drm,
				"Date lane not in STOP state\n");
	}

	/* Wait for AFE LATCH */
	for_each_dsi_port(port, intel_dsi->ports) {
		if (intel_de_wait_for_set_ms(display, BXT_MIPI_PORT_CTRL(port),
					     AFE_LATCHOUT, 20))
			drm_err(display->drm,
				"D-PHY not entering LP-11 state\n");
	}
}

static void bxt_dsi_device_ready(struct intel_encoder *encoder)
{
	struct intel_display *display = to_intel_display(encoder);
	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
	enum port port;
	u32 val;

	drm_dbg_kms(display->drm, "\n");

	/* Enable MIPI PHY transparent latch */
	for_each_dsi_port(port, intel_dsi->ports) {
		intel_de_rmw(display, BXT_MIPI_PORT_CTRL(port), 0, LP_OUTPUT_HOLD);
		usleep_range(2000, 2500);
	}

	/* Clear ULPS and set device ready */
	for_each_dsi_port(port, intel_dsi->ports) {
		val = intel_de_read(display, MIPI_DEVICE_READY(display, port));
		val &= ~ULPS_STATE_MASK;
		intel_de_write(display, MIPI_DEVICE_READY(display, port), val);
		usleep_range(2000, 2500);
		val |= DEVICE_READY;
		intel_de_write(display, MIPI_DEVICE_READY(display, port), val);
	}
}

static void vlv_dsi_device_ready(struct intel_encoder *encoder)
{
	struct intel_display *display = to_intel_display(encoder);
	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
	enum port port;

	drm_dbg_kms(display->drm, "\n");

	vlv_flisdsi_get(display);
	/* program rcomp for compliance, reduce from 50 ohms to 45 ohms
	 * needed everytime after power gate */
	vlv_flisdsi_write(display, 0x04, 0x0004);
	vlv_flisdsi_put(display);

	/* bandgap reset is needed after everytime we do power gate */
	band_gap_reset(display);

	for_each_dsi_port(port, intel_dsi->ports) {

		intel_de_write(display, MIPI_DEVICE_READY(display, port),

Annotation

Implementation Notes