drivers/gpu/drm/i915/gt/gen8_engine_cs.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/i915/gt/gen8_engine_cs.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/i915/gt/gen8_engine_cs.c
Extension
.c
Size
22879 bytes
Lines
856
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

IS_DG2(rq->i915)) {
		u32 *cs;

		/* dummy PIPE_CONTROL + depth flush */
		cs = intel_ring_begin(rq, 6);
		if (IS_ERR(cs))
			return PTR_ERR(cs);
		cs = gen12_emit_pipe_control(cs,
					     0,
					     PIPE_CONTROL_DEPTH_CACHE_FLUSH,
					     LRC_PPHWSP_SCRATCH_ADDR);
		intel_ring_advance(rq, cs);
	}

	return 0;
}

int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
{
	struct intel_engine_cs *engine = rq->engine;

	/*
	 * On Aux CCS platforms the invalidation of the Aux
	 * table requires quiescing memory traffic beforehand
	 */
	if (mode & EMIT_FLUSH || gen12_needs_ccs_aux_inv(engine)) {
		u32 bit_group_0 = 0;
		u32 bit_group_1 = 0;
		int err;
		u32 *cs;

		err = mtl_dummy_pipe_control(rq);
		if (err)
			return err;

		bit_group_0 |= PIPE_CONTROL0_HDC_PIPELINE_FLUSH;

		/*
		 * When required, in MTL and beyond platforms we
		 * need to set the CCS_FLUSH bit in the pipe control
		 */
		if (GRAPHICS_VER_FULL(rq->i915) >= IP_VER(12, 70))
			bit_group_0 |= PIPE_CONTROL_CCS_FLUSH;

		/*
		 * L3 fabric flush is needed for AUX CCS invalidation
		 * which happens as part of pipe-control so we can
		 * ignore PIPE_CONTROL_FLUSH_L3. Also PIPE_CONTROL_FLUSH_L3
		 * deals with Protected Memory which is not needed for
		 * AUX CCS invalidation and lead to unwanted side effects.
		 */
		if ((mode & EMIT_FLUSH) &&
		    GRAPHICS_VER_FULL(rq->i915) < IP_VER(12, 70))
			bit_group_1 |= PIPE_CONTROL_FLUSH_L3;

		bit_group_1 |= PIPE_CONTROL_TILE_CACHE_FLUSH;
		bit_group_1 |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
		bit_group_1 |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
		/* Wa_1409600907:tgl,adl-p */
		bit_group_1 |= PIPE_CONTROL_DEPTH_STALL;
		bit_group_1 |= PIPE_CONTROL_DC_FLUSH_ENABLE;
		bit_group_1 |= PIPE_CONTROL_FLUSH_ENABLE;

		bit_group_1 |= PIPE_CONTROL_STORE_DATA_INDEX;
		bit_group_1 |= PIPE_CONTROL_QW_WRITE;

		bit_group_1 |= PIPE_CONTROL_CS_STALL;

		if (!HAS_3D_PIPELINE(engine->i915))
			bit_group_1 &= ~PIPE_CONTROL_3D_ARCH_FLAGS;
		else if (engine->class == COMPUTE_CLASS)
			bit_group_1 &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;

		cs = intel_ring_begin(rq, 6);
		if (IS_ERR(cs))
			return PTR_ERR(cs);

		cs = gen12_emit_pipe_control(cs, bit_group_0, bit_group_1,
					     LRC_PPHWSP_SCRATCH_ADDR);
		intel_ring_advance(rq, cs);
	}

	if (mode & EMIT_INVALIDATE) {
		u32 flags = 0;
		u32 *cs, count;
		int err;

		err = mtl_dummy_pipe_control(rq);
		if (err)
			return err;

Annotation

Implementation Notes