drivers/gpu/drm/i915/gt/intel_engine_cs.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/i915/gt/intel_engine_cs.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/i915/gt/intel_engine_cs.c- Extension
.c- Size
- 71135 bytes
- Lines
- 2563
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/string_helpers.hdrm/drm_print.hgem/i915_gem_context.hgem/i915_gem_internal.hgt/intel_gt_print.hgt/intel_gt_regs.hi915_cmd_parser.hi915_drv.hi915_irq.hi915_reg.hintel_breadcrumbs.hintel_context.hintel_engine.hintel_engine_pm.hintel_engine_regs.hintel_engine_user.hintel_execlists_submission.hintel_gt.hintel_gt_mcr.hintel_gt_pm.hintel_gt_requests.hintel_lrc.hintel_lrc_reg.hintel_reset.hintel_ring.huc/intel_guc_submission.hmock_engine.cselftest_engine.cselftest_engine_cs.c
Detected Declarations
struct engine_infostruct engine_mmio_basestruct measure_breadcrumbfunction intel_engine_context_sizefunction __engine_mmio_basefunction __sprint_engine_namefunction intel_engine_set_hwsp_writemaskfunction intel_engine_sanitize_mmiofunction nop_irq_handlerfunction get_reset_domainfunction intel_engine_setupfunction intel_clamp_heartbeat_interval_msfunction intel_clamp_max_busywait_duration_nsfunction intel_clamp_preempt_timeout_msfunction intel_clamp_stop_timeout_msfunction intel_clamp_timeslice_duration_msfunction __setup_engine_capabilitiesfunction intel_setup_engine_capabilitiesfunction intel_engines_releasefunction intel_engine_free_request_poolfunction intel_engines_freefunction for_each_enginefunction gen11_vdbox_has_sfcfunction engine_mask_apply_media_fusesfunction engine_mask_apply_compute_fusesfunction init_engine_maskfunction populate_logical_idsfunction setup_logical_idsfunction intel_engines_init_mmiofunction intel_engine_init_execlistsfunction cleanup_status_pagefunction pin_ggtt_status_pagefunction init_status_pagefunction intel_engine_init_tlb_invalidationfunction GRAPHICS_VER_FULLfunction engine_setup_commonfunction measure_breadcrumb_dwfunction intel_engine_create_pinned_contextfunction intel_engine_destroy_pinned_contextfunction create_ggtt_bind_contextfunction create_kernel_contextfunction engine_init_commonfunction intel_engines_initfunction for_each_enginefunction intel_engine_cleanup_commonfunction intel_engine_resumefunction intel_engine_get_active_headfunction intel_engine_get_last_batch_head
Annotated Snippet
struct engine_info {
u8 class;
u8 instance;
/* mmio bases table *must* be sorted in reverse graphics_ver order */
struct engine_mmio_base {
u32 graphics_ver : 8;
u32 base : 24;
} mmio_bases[MAX_MMIO_BASES];
};
static const struct engine_info intel_engines[] = {
[RCS0] = {
.class = RENDER_CLASS,
.instance = 0,
.mmio_bases = {
{ .graphics_ver = 1, .base = RENDER_RING_BASE }
},
},
[BCS0] = {
.class = COPY_ENGINE_CLASS,
.instance = 0,
.mmio_bases = {
{ .graphics_ver = 6, .base = BLT_RING_BASE }
},
},
[BCS1] = {
.class = COPY_ENGINE_CLASS,
.instance = 1,
.mmio_bases = {
{ .graphics_ver = 12, .base = XEHPC_BCS1_RING_BASE }
},
},
[BCS2] = {
.class = COPY_ENGINE_CLASS,
.instance = 2,
.mmio_bases = {
{ .graphics_ver = 12, .base = XEHPC_BCS2_RING_BASE }
},
},
[BCS3] = {
.class = COPY_ENGINE_CLASS,
.instance = 3,
.mmio_bases = {
{ .graphics_ver = 12, .base = XEHPC_BCS3_RING_BASE }
},
},
[BCS4] = {
.class = COPY_ENGINE_CLASS,
.instance = 4,
.mmio_bases = {
{ .graphics_ver = 12, .base = XEHPC_BCS4_RING_BASE }
},
},
[BCS5] = {
.class = COPY_ENGINE_CLASS,
.instance = 5,
.mmio_bases = {
{ .graphics_ver = 12, .base = XEHPC_BCS5_RING_BASE }
},
},
[BCS6] = {
.class = COPY_ENGINE_CLASS,
.instance = 6,
.mmio_bases = {
{ .graphics_ver = 12, .base = XEHPC_BCS6_RING_BASE }
},
},
[BCS7] = {
.class = COPY_ENGINE_CLASS,
.instance = 7,
.mmio_bases = {
{ .graphics_ver = 12, .base = XEHPC_BCS7_RING_BASE }
},
},
[BCS8] = {
.class = COPY_ENGINE_CLASS,
.instance = 8,
.mmio_bases = {
{ .graphics_ver = 12, .base = XEHPC_BCS8_RING_BASE }
},
},
[VCS0] = {
.class = VIDEO_DECODE_CLASS,
.instance = 0,
.mmio_bases = {
{ .graphics_ver = 11, .base = GEN11_BSD_RING_BASE },
{ .graphics_ver = 6, .base = GEN6_BSD_RING_BASE },
{ .graphics_ver = 4, .base = BSD_RING_BASE }
},
},
Annotation
- Immediate include surface: `linux/string_helpers.h`, `drm/drm_print.h`, `gem/i915_gem_context.h`, `gem/i915_gem_internal.h`, `gt/intel_gt_print.h`, `gt/intel_gt_regs.h`, `i915_cmd_parser.h`, `i915_drv.h`.
- Detected declarations: `struct engine_info`, `struct engine_mmio_base`, `struct measure_breadcrumb`, `function intel_engine_context_size`, `function __engine_mmio_base`, `function __sprint_engine_name`, `function intel_engine_set_hwsp_writemask`, `function intel_engine_sanitize_mmio`, `function nop_irq_handler`, `function get_reset_domain`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.