drivers/gpu/drm/i915/gt/intel_engine_regs.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/i915/gt/intel_engine_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/i915/gt/intel_engine_regs.h
Extension
.h
Size
12482 bytes
Lines
270
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __INTEL_ENGINE_REGS__
#define __INTEL_ENGINE_REGS__

#include "i915_reg_defs.h"

#define RING_EXCC(base)				_MMIO((base) + 0x28)
#define RING_TAIL(base)				_MMIO((base) + 0x30)
#define   TAIL_ADDR				0x001FFFF8
#define RING_HEAD(base)				_MMIO((base) + 0x34)
#define   HEAD_WRAP_COUNT			0xFFE00000
#define   HEAD_WRAP_ONE				0x00200000
#define   HEAD_ADDR				0x001FFFFC
#define   HEAD_WAIT_I8XX			(1 << 0) /* gen2, PRBx_HEAD */
#define RING_START(base)			_MMIO((base) + 0x38)
#define RING_CTL(base)				_MMIO((base) + 0x3c)
#define   RING_CTL_SIZE(size)			((size) - PAGE_SIZE) /* in bytes -> pages */
#define   RING_NR_PAGES				0x001FF000
#define   RING_REPORT_MASK			0x00000006
#define   RING_REPORT_64K			0x00000002
#define   RING_REPORT_128K			0x00000004
#define   RING_NO_REPORT			0x00000000
#define   RING_VALID_MASK			0x00000001
#define   RING_VALID				0x00000001
#define   RING_INVALID				0x00000000
#define   RING_WAIT				(1 << 11) /* gen3+, PRBx_CTL */
#define   RING_WAIT_SEMAPHORE			(1 << 10) /* gen6+ */
#define RING_SYNC_0(base)			_MMIO((base) + 0x40)
#define RING_SYNC_1(base)			_MMIO((base) + 0x44)
#define RING_SYNC_2(base)			_MMIO((base) + 0x48)
#define GEN6_RVSYNC				(RING_SYNC_0(RENDER_RING_BASE))
#define GEN6_RBSYNC				(RING_SYNC_1(RENDER_RING_BASE))
#define GEN6_RVESYNC				(RING_SYNC_2(RENDER_RING_BASE))
#define GEN6_VBSYNC				(RING_SYNC_0(GEN6_BSD_RING_BASE))
#define GEN6_VRSYNC				(RING_SYNC_1(GEN6_BSD_RING_BASE))
#define GEN6_VVESYNC				(RING_SYNC_2(GEN6_BSD_RING_BASE))
#define GEN6_BRSYNC				(RING_SYNC_0(BLT_RING_BASE))
#define GEN6_BVSYNC				(RING_SYNC_1(BLT_RING_BASE))
#define GEN6_BVESYNC				(RING_SYNC_2(BLT_RING_BASE))
#define GEN6_VEBSYNC				(RING_SYNC_0(VEBOX_RING_BASE))
#define GEN6_VERSYNC				(RING_SYNC_1(VEBOX_RING_BASE))
#define GEN6_VEVSYNC				(RING_SYNC_2(VEBOX_RING_BASE))
#define RING_PSMI_CTL(base)			_MMIO((base) + 0x50)
#define   GEN8_RC_SEMA_IDLE_MSG_DISABLE		REG_BIT(12)
#define   GEN8_FF_DOP_CLOCK_GATE_DISABLE	REG_BIT(10)
#define   GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)
#define   GEN6_BSD_GO_INDICATOR			REG_BIT(4)
#define   GEN6_BSD_SLEEP_INDICATOR		REG_BIT(3)
#define   GEN6_BSD_SLEEP_FLUSH_DISABLE		REG_BIT(2)
#define   GEN6_PSMI_SLEEP_MSG_DISABLE		REG_BIT(0)
#define RING_MAX_IDLE(base)			_MMIO((base) + 0x54)
#define  PWRCTX_MAXCNT(base)			_MMIO((base) + 0x54)
#define    IDLE_TIME_MASK			0xFFFFF
#define RING_ACTHD_UDW(base)			_MMIO((base) + 0x5c)
#define RING_DMA_FADD_UDW(base)			_MMIO((base) + 0x60) /* gen8+ */
#define RING_IPEIR(base)			_MMIO((base) + 0x64)
#define RING_IPEHR(base)			_MMIO((base) + 0x68)
#define RING_INSTDONE(base)			_MMIO((base) + 0x6c)
#define RING_INSTPS(base)			_MMIO((base) + 0x70)
#define RING_DMA_FADD(base)			_MMIO((base) + 0x78)
#define RING_ACTHD(base)			_MMIO((base) + 0x74)
#define RING_HWS_PGA(base)			_MMIO((base) + 0x80)
#define RING_CMD_BUF_CCTL(base)			_MMIO((base) + 0x84)
#define IPEIR(base)				_MMIO((base) + 0x88)
#define IPEHR(base)				_MMIO((base) + 0x8c)
#define RING_ID(base)				_MMIO((base) + 0x8c)
#define RING_NOPID(base)			_MMIO((base) + 0x94)
#define RING_HWSTAM(base)			_MMIO((base) + 0x98)
#define RING_MI_MODE(base)			_MMIO((base) + 0x9c)
#define   ASYNC_FLIP_PERF_DISABLE		REG_BIT(14)
#define   MI_FLUSH_ENABLE			REG_BIT(12)
#define   TGL_NESTED_BB_EN			REG_BIT(12)
#define   MODE_IDLE				REG_BIT(9)
#define   STOP_RING				REG_BIT(8)
#define   VS_TIMER_DISPATCH			REG_BIT(6)
#define RING_IMR(base)				_MMIO((base) + 0xa8)
#define RING_EIR(base)				_MMIO((base) + 0xb0)
#define RING_EMR(base)				_MMIO((base) + 0xb4)
#define RING_ESR(base)				_MMIO((base) + 0xb8)
#define GEN12_STATE_ACK_DEBUG(base)		_MMIO((base) + 0xbc)
#define RING_INSTPM(base)			_MMIO((base) + 0xc0)
#define RING_CMD_CCTL(base)			_MMIO((base) + 0xc4)
#define ACTHD(base)				_MMIO((base) + 0xc8)
#define GEN8_R_PWR_CLK_STATE(base)		_MMIO((base) + 0xc8)
#define   GEN8_RPCS_ENABLE			(1 << 31)
#define   GEN8_RPCS_S_CNT_ENABLE		(1 << 18)
#define   GEN8_RPCS_S_CNT_SHIFT			15
#define   GEN8_RPCS_S_CNT_MASK			(0x7 << GEN8_RPCS_S_CNT_SHIFT)
#define   GEN11_RPCS_S_CNT_SHIFT		12
#define   GEN11_RPCS_S_CNT_MASK			(0x3f << GEN11_RPCS_S_CNT_SHIFT)
#define   GEN8_RPCS_SS_CNT_ENABLE		(1 << 11)

Annotation

Implementation Notes