drivers/gpu/drm/i915/gt/intel_ggtt_gmch.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/i915/gt/intel_ggtt_gmch.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/i915/gt/intel_ggtt_gmch.c- Extension
.c- Size
- 3417 bytes
- Lines
- 141
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
intel_ggtt_gmch.hdrm/drm_print.hdrm/intel/intel-gtt.hlinux/agp_backend.hi915_drv.hi915_utils.hintel_gtt.hintel_gt_regs.hintel_gt.h
Detected Declarations
function gmch_ggtt_insert_pagefunction gmch_ggtt_read_entryfunction gmch_ggtt_insert_entriesfunction gmch_ggtt_invalidatefunction gmch_ggtt_clear_rangefunction gmch_ggtt_removefunction needs_idle_mapsfunction intel_ggtt_gmch_probefunction intel_ggtt_gmch_enable_hwfunction intel_ggtt_gmch_flush
Annotated Snippet
// SPDX-License-Identifier: MIT
/*
* Copyright © 2022 Intel Corporation
*/
#include "intel_ggtt_gmch.h"
#include <drm/drm_print.h>
#include <drm/intel/intel-gtt.h>
#include <linux/agp_backend.h>
#include "i915_drv.h"
#include "i915_utils.h"
#include "intel_gtt.h"
#include "intel_gt_regs.h"
#include "intel_gt.h"
static void gmch_ggtt_insert_page(struct i915_address_space *vm,
dma_addr_t addr,
u64 offset,
unsigned int pat_index,
u32 unused)
{
unsigned int flags = (pat_index == I915_CACHE_NONE) ?
AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
intel_gmch_gtt_insert_page(addr, offset >> PAGE_SHIFT, flags);
}
static dma_addr_t gmch_ggtt_read_entry(struct i915_address_space *vm,
u64 offset, bool *is_present, bool *is_local)
{
return intel_gmch_gtt_read_entry(offset >> PAGE_SHIFT,
is_present, is_local);
}
static void gmch_ggtt_insert_entries(struct i915_address_space *vm,
struct i915_vma_resource *vma_res,
unsigned int pat_index,
u32 unused)
{
unsigned int flags = (pat_index == I915_CACHE_NONE) ?
AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
intel_gmch_gtt_insert_sg_entries(vma_res->bi.pages, vma_res->start >> PAGE_SHIFT,
flags);
}
static void gmch_ggtt_invalidate(struct i915_ggtt *ggtt)
{
intel_gmch_gtt_flush();
}
static void gmch_ggtt_clear_range(struct i915_address_space *vm,
u64 start, u64 length)
{
intel_gmch_gtt_clear_range(start >> PAGE_SHIFT, length >> PAGE_SHIFT);
}
static void gmch_ggtt_remove(struct i915_address_space *vm)
{
intel_gmch_remove();
}
/*
* Certain Gen5 chipsets require idling the GPU before unmapping anything from
* the GTT when VT-d is enabled.
*/
static bool needs_idle_maps(struct drm_i915_private *i915)
{
/*
* Query intel_iommu to see if we need the workaround. Presumably that
* was loaded first.
*/
if (!i915_vtd_active(i915))
return false;
if (GRAPHICS_VER(i915) == 5 && IS_MOBILE(i915))
return true;
return false;
}
int intel_ggtt_gmch_probe(struct i915_ggtt *ggtt)
{
struct drm_i915_private *i915 = ggtt->vm.i915;
phys_addr_t gmadr_base;
int ret;
Annotation
- Immediate include surface: `intel_ggtt_gmch.h`, `drm/drm_print.h`, `drm/intel/intel-gtt.h`, `linux/agp_backend.h`, `i915_drv.h`, `i915_utils.h`, `intel_gtt.h`, `intel_gt_regs.h`.
- Detected declarations: `function gmch_ggtt_insert_page`, `function gmch_ggtt_read_entry`, `function gmch_ggtt_insert_entries`, `function gmch_ggtt_invalidate`, `function gmch_ggtt_clear_range`, `function gmch_ggtt_remove`, `function needs_idle_maps`, `function intel_ggtt_gmch_probe`, `function intel_ggtt_gmch_enable_hw`, `function intel_ggtt_gmch_flush`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.