drivers/gpu/drm/i915/gt/intel_gt_regs.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/i915/gt/intel_gt_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/i915/gt/intel_gt_regs.h
Extension
.h
Size
65593 bytes
Lines
1643
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __INTEL_GT_REGS__
#define __INTEL_GT_REGS__

#include "i915_reg_defs.h"

#define VLV_GUNIT_BASE			0x180000

/*
 * The perf control registers are technically multicast registers, but the
 * driver never needs to read/write them directly; we only use them to build
 * lists of registers (where they're mixed in with other non-MCR registers)
 * and then operate on the offset directly.  For now we'll just define them
 * as non-multicast so we can place them on the same list, but we may want
 * to try to come up with a better way to handle heterogeneous lists of
 * registers in the future.
 */
#define PERF_REG(offset)			_MMIO(offset)

/* MTL workpoint reg to get core C state and actual freq of 3D, SAMedia */
#define MTL_MIRROR_TARGET_WP1			_MMIO(0xc60)
#define   MTL_CAGF_MASK				REG_GENMASK(8, 0)
#define   MTL_CC0				0x0
#define   MTL_CC6				0x3
#define   MTL_CC_MASK				REG_GENMASK(10, 9)

/* RPM unit config (Gen8+) */
#define RPM_CONFIG0				_MMIO(0xd00)
#define   GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK	REG_GENMASK(5, 3)
#define   GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ	REG_FIELD_PREP(GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 0)
#define   GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ	REG_FIELD_PREP(GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 1)
#define   GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ	REG_FIELD_PREP(GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 2)
#define   GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ	REG_FIELD_PREP(GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 3)
#define   GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK	REG_BIT(3)
#define   GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ	REG_FIELD_PREP(GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 0)
#define   GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ	REG_FIELD_PREP(GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 1)
#define   GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK	REG_GENMASK(2, 1)

#define RPM_CONFIG1				_MMIO(0xd04)
#define   GEN10_GT_NOA_ENABLE			(1 << 9)

/* RCP unit config (Gen8+) */
#define RCP_CONFIG				_MMIO(0xd08)

#define RC6_LOCATION				_MMIO(0xd40)
#define   RC6_CTX_IN_DRAM			(1 << 0)
#define RC6_CTX_BASE				_MMIO(0xd48)
#define   RC6_CTX_BASE_MASK			0xFFFFFFF0

#define FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(n)	_MMIO(0xd50 + (n) * 4)
#define FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(n)	_MMIO(0xd70 + (n) * 4)
#define FORCEWAKE_ACK_RENDER_GEN9		_MMIO(0xd84)
#define FORCEWAKE_ACK_MEDIA_GEN9		_MMIO(0xd88)

#define FORCEWAKE_ACK_GSC			_MMIO(0xdf8)
#define FORCEWAKE_ACK_GT_MTL			_MMIO(0xdfc)

#define GMD_ID_GRAPHICS				_MMIO(0xd8c)
#define GMD_ID_MEDIA				_MMIO(MTL_MEDIA_GSI_BASE + 0xd8c)
#define   GMD_ID_ARCH_MASK			REG_GENMASK(31, 22)
#define   GMD_ID_RELEASE_MASK			REG_GENMASK(21, 14)
#define   GMD_ID_STEP				REG_GENMASK(5, 0)

#define MCFG_MCR_SELECTOR			_MMIO(0xfd0)
#define MTL_STEER_SEMAPHORE			_MMIO(0xfd0)
#define MTL_MCR_SELECTOR			_MMIO(0xfd4)
#define SF_MCR_SELECTOR				_MMIO(0xfd8)
#define GEN8_MCR_SELECTOR			_MMIO(0xfdc)
#define GAM_MCR_SELECTOR			_MMIO(0xfe0)
#define   GEN8_MCR_SLICE(slice)			(((slice) & 3) << 26)
#define   GEN8_MCR_SLICE_MASK			GEN8_MCR_SLICE(3)
#define   GEN8_MCR_SUBSLICE(subslice)		(((subslice) & 3) << 24)
#define   GEN8_MCR_SUBSLICE_MASK		GEN8_MCR_SUBSLICE(3)
#define   GEN11_MCR_MULTICAST			REG_BIT(31)
#define   GEN11_MCR_SLICE(slice)		(((slice) & 0xf) << 27)
#define   GEN11_MCR_SLICE_MASK			GEN11_MCR_SLICE(0xf)
#define   GEN11_MCR_SUBSLICE(subslice)		(((subslice) & 0x7) << 24)
#define   GEN11_MCR_SUBSLICE_MASK		GEN11_MCR_SUBSLICE(0x7)
#define   MTL_MCR_GROUPID			REG_GENMASK(11, 8)
#define   MTL_MCR_INSTANCEID			REG_GENMASK(3, 0)

#define IPEIR_I965				_MMIO(0x2064)
#define IPEHR_I965				_MMIO(0x2068)

/*
 * On GEN4, only the render ring INSTDONE exists and has a different
 * layout than the GEN7+ version.
 * The GEN2 counterpart of this register is GEN2_INSTDONE.
 */
#define INSTPS					_MMIO(0x2070) /* 965+ only */
#define GEN4_INSTDONE1				_MMIO(0x207c) /* 965+ only, aka INSTDONE_2 on SNB */

Annotation

Implementation Notes