drivers/gpu/drm/i915/gt/intel_ring_submission.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/i915/gt/intel_ring_submission.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/i915/gt/intel_ring_submission.c
Extension
.c
Size
38813 bytes
Lines
1460
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

switch (engine->id) {
		/*
		 * No more rings exist on Gen7. Default case is only to shut up
		 * gcc switch check warning.
		 */
		default:
			GEM_BUG_ON(engine->id);
			fallthrough;
		case RCS0:
			hwsp = RENDER_HWS_PGA_GEN7;
			break;
		case BCS0:
			hwsp = BLT_HWS_PGA_GEN7;
			break;
		case VCS0:
			hwsp = BSD_HWS_PGA_GEN7;
			break;
		case VECS0:
			hwsp = VEBOX_HWS_PGA_GEN7;
			break;
		}
	} else if (GRAPHICS_VER(engine->i915) == 6) {
		hwsp = RING_HWS_PGA_GEN6(engine->mmio_base);
	} else {
		hwsp = RING_HWS_PGA(engine->mmio_base);
	}

	intel_uncore_write_fw(engine->uncore, hwsp, offset);
	intel_uncore_posting_read_fw(engine->uncore, hwsp);
}

static void flush_cs_tlb(struct intel_engine_cs *engine)
{
	if (!IS_GRAPHICS_VER(engine->i915, 6, 7))
		return;

	/* ring should be idle before issuing a sync flush*/
	if ((ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0)
		drm_warn(&engine->i915->drm, "%s not idle before sync flush!\n",
			 engine->name);

	ENGINE_WRITE_FW(engine, RING_INSTPM,
			REG_MASKED_FIELD_ENABLE(INSTPM_TLB_INVALIDATE | INSTPM_SYNC_FLUSH));
	if (__intel_wait_for_register_fw(engine->uncore,
					 RING_INSTPM(engine->mmio_base),
					 INSTPM_SYNC_FLUSH, 0,
					 2000, 0, NULL))
		ENGINE_TRACE(engine,
			     "wait for SyncFlush to complete for TLB invalidation timed out\n");
}

static void ring_setup_status_page(struct intel_engine_cs *engine)
{
	set_hwsp(engine, i915_ggtt_offset(engine->status_page.vma));
	set_hwstam(engine, ~0u);

	flush_cs_tlb(engine);
}

static struct i915_address_space *vm_alias(struct i915_address_space *vm)
{
	if (i915_is_ggtt(vm))
		vm = &i915_vm_to_ggtt(vm)->alias->vm;

	return vm;
}

static u32 pp_dir(struct i915_address_space *vm)
{
	return to_gen6_ppgtt(i915_vm_to_ppgtt(vm))->pp_dir;
}

static void set_pp_dir(struct intel_engine_cs *engine)
{
	struct i915_address_space *vm = vm_alias(engine->gt->vm);

	if (!vm)
		return;

	ENGINE_WRITE_FW(engine, RING_PP_DIR_DCLV, PP_DIR_DCLV_2G);
	ENGINE_WRITE_FW(engine, RING_PP_DIR_BASE, pp_dir(vm));

	if (GRAPHICS_VER(engine->i915) >= 7) {
		ENGINE_WRITE_FW(engine,
				RING_MODE_GEN7,
				REG_MASKED_FIELD_ENABLE(GFX_PPGTT_ENABLE));
	}
}

static bool stop_ring(struct intel_engine_cs *engine)

Annotation

Implementation Notes