drivers/gpu/drm/i915/gt/intel_wopcm.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/i915/gt/intel_wopcm.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/i915/gt/intel_wopcm.c
Extension
.c
Size
10533 bytes
Lines
322
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (unlikely(guc_wopcm_base < size)) {
			drm_err(&i915->drm, "WOPCM: no space for %s: %uK < %uK\n",
				intel_uc_fw_type_repr(INTEL_UC_FW_TYPE_HUC),
				guc_wopcm_base / SZ_1K, size / SZ_1K);
			return false;
		}
	}

	return check_hw_restrictions(i915, guc_wopcm_base, guc_wopcm_size,
				     huc_fw_size);
}

static bool __wopcm_regs_locked(struct intel_uncore *uncore,
				u32 *guc_wopcm_base, u32 *guc_wopcm_size)
{
	u32 reg_base = intel_uncore_read(uncore, DMA_GUC_WOPCM_OFFSET);
	u32 reg_size = intel_uncore_read(uncore, GUC_WOPCM_SIZE);

	if (!(reg_size & GUC_WOPCM_SIZE_LOCKED) ||
	    !(reg_base & GUC_WOPCM_OFFSET_VALID))
		return false;

	*guc_wopcm_base = reg_base & GUC_WOPCM_OFFSET_MASK;
	*guc_wopcm_size = reg_size & GUC_WOPCM_SIZE_MASK;
	return true;
}

static bool __wopcm_regs_writable(struct intel_uncore *uncore)
{
	if (!HAS_GUC_DEPRIVILEGE(uncore->i915))
		return true;

	return intel_uncore_read(uncore, GUC_SHIM_CONTROL2) & GUC_IS_PRIVILEGED;
}

/**
 * intel_wopcm_init() - Initialize the WOPCM structure.
 * @wopcm: pointer to intel_wopcm.
 *
 * This function will partition WOPCM space based on GuC and HuC firmware sizes
 * and will allocate max remaining for use by GuC. This function will also
 * enforce platform dependent hardware restrictions on GuC WOPCM offset and
 * size. It will fail the WOPCM init if any of these checks fail, so that the
 * following WOPCM registers setup and GuC firmware uploading would be aborted.
 */
void intel_wopcm_init(struct intel_wopcm *wopcm)
{
	struct intel_gt *gt = wopcm_to_gt(wopcm);
	struct drm_i915_private *i915 = gt->i915;
	u32 guc_fw_size = intel_uc_fw_get_upload_size(&gt->uc.guc.fw);
	u32 huc_fw_size = intel_uc_fw_get_upload_size(&gt->uc.huc.fw);
	u32 ctx_rsvd = context_reserved_size(i915);
	u32 wopcm_size = wopcm->size;
	u32 guc_wopcm_base;
	u32 guc_wopcm_size;

	if (!guc_fw_size)
		return;

	GEM_BUG_ON(!wopcm_size);
	GEM_BUG_ON(wopcm->guc.base);
	GEM_BUG_ON(wopcm->guc.size);
	GEM_BUG_ON(guc_fw_size >= wopcm_size);
	GEM_BUG_ON(huc_fw_size >= wopcm_size);
	GEM_BUG_ON(ctx_rsvd + WOPCM_RESERVED_SIZE >= wopcm_size);

	if (__wopcm_regs_locked(gt->uncore, &guc_wopcm_base, &guc_wopcm_size)) {
		drm_dbg(&i915->drm, "GuC WOPCM is already locked [%uK, %uK)\n",
			guc_wopcm_base / SZ_1K, guc_wopcm_size / SZ_1K);
		/*
		 * Note that to keep things simple (i.e. avoid different
		 * defines per platform) our WOPCM math doesn't always use the
		 * actual WOPCM size, but a value that is less or equal to it.
		 * This is perfectly fine when i915 programs the registers, but
		 * on platforms with GuC deprivilege the registers are not
		 * writable from i915 and are instead pre-programmed by the
		 * bios/IFWI, so there might be a mismatch of sizes.
		 * Instead of handling the size difference, we trust that the
		 * programmed values make sense and disable the relevant check
		 * by using the maximum possible WOPCM size in the verification
		 * math. In the extremely unlikely case that the registers
		 * were pre-programmed with an invalid value, we will still
		 * gracefully fail later during the GuC/HuC dma.
		 */
		if (!__wopcm_regs_writable(gt->uncore))
			wopcm_size = MAX_WOPCM_SIZE;

		goto check;
	}

Annotation

Implementation Notes