drivers/gpu/drm/i915/gt/intel_workarounds.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/i915/gt/intel_workarounds.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/i915/gt/intel_workarounds.c- Extension
.c- Size
- 92666 bytes
- Lines
- 3132
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
drm/intel/intel_gmd_misc_regs.hi915_drv.hi915_reg.hi915_mmio_range.hintel_context.hintel_engine_pm.hintel_engine_regs.hintel_gpu_commands.hintel_gt.hintel_gt_ccs_mode.hintel_gt_mcr.hintel_gt_print.hintel_gt_regs.hintel_ring.hintel_workarounds.hdisplay/intel_fbc_regs.hselftest_workarounds.c
Detected Declarations
function xcs_engine_wa_initfunction wa_init_finishfunction wal_get_fw_for_rmwfunction _wa_addfunction wa_addfunction wa_mcr_addfunction wa_write_clr_setfunction wa_mcr_write_clr_setfunction wa_writefunction wa_write_orfunction wa_mcr_write_orfunction wa_write_clrfunction wa_mcr_write_clrfunction wa_masked_enfunction wa_mcr_masked_enfunction wa_masked_disfunction wa_mcr_masked_disfunction wa_masked_field_setfunction wa_mcr_masked_field_setfunction gen6_ctx_workarounds_initfunction gen7_ctx_workarounds_initfunction gen8_ctx_workarounds_initfunction bdw_ctx_workarounds_initfunction chv_ctx_workarounds_initfunction gen9_ctx_workarounds_initfunction skl_tune_iz_hashingfunction skl_ctx_workarounds_initfunction bxt_ctx_workarounds_initfunction kbl_ctx_workarounds_initfunction glk_ctx_workarounds_initfunction cfl_ctx_workarounds_initfunction icl_ctx_workarounds_initfunction dg2_ctx_gt_tuning_initfunction gen12_ctx_workarounds_initfunction dg1_ctx_workarounds_initfunction dg2_ctx_workarounds_initfunction xelpg_ctx_gt_tuning_initfunction xelpg_ctx_workarounds_initfunction fakewa_disable_nestedbb_modefunction gen12_ctx_gt_mocs_initfunction gen12_ctx_gt_fake_wa_initfunction __intel_engine_init_ctx_wafunction intel_engine_init_ctx_wafunction intel_engine_emit_ctx_wafunction IS_DG2function gen4_gt_workarounds_initfunction g4x_gt_workarounds_initfunction ilk_gt_workarounds_init
Annotated Snippet
if (list) {
kfree(wal->list);
wal->list = list;
}
}
if (!wal->count)
return;
gt_dbg(wal->gt, "Initialized %u %s workarounds on %s\n",
wal->wa_count, wal->name, wal->engine_name);
}
static enum forcewake_domains
wal_get_fw_for_rmw(struct intel_uncore *uncore, const struct i915_wa_list *wal)
{
enum forcewake_domains fw = 0;
struct i915_wa *wa;
unsigned int i;
for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
fw |= intel_uncore_forcewake_for_reg(uncore,
wa->reg,
FW_REG_READ |
FW_REG_WRITE);
return fw;
}
static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa)
{
unsigned int addr = i915_mmio_reg_offset(wa->reg);
struct drm_i915_private *i915 = wal->gt->i915;
unsigned int start = 0, end = wal->count;
const unsigned int grow = WA_LIST_CHUNK;
struct i915_wa *wa_;
GEM_BUG_ON(!is_power_of_2(grow));
if (IS_ALIGNED(wal->count, grow)) { /* Either uninitialized or full. */
struct i915_wa *list;
list = kmalloc_objs(*list, ALIGN(wal->count + 1, grow));
if (!list) {
drm_err(&i915->drm, "No space for workaround init!\n");
return;
}
if (wal->list) {
memcpy(list, wal->list, sizeof(*wa) * wal->count);
kfree(wal->list);
}
wal->list = list;
}
while (start < end) {
unsigned int mid = start + (end - start) / 2;
if (i915_mmio_reg_offset(wal->list[mid].reg) < addr) {
start = mid + 1;
} else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) {
end = mid;
} else {
wa_ = &wal->list[mid];
if ((wa->clr | wa_->clr) && !(wa->clr & ~wa_->clr)) {
drm_err(&i915->drm,
"Discarding overwritten w/a for reg %04x (clear: %08x, set: %08x)\n",
i915_mmio_reg_offset(wa_->reg),
wa_->clr, wa_->set);
wa_->set &= ~wa->clr;
}
wal->wa_count++;
wa_->set |= wa->set;
wa_->clr |= wa->clr;
wa_->read |= wa->read;
return;
}
}
wal->wa_count++;
wa_ = &wal->list[wal->count++];
*wa_ = *wa;
while (wa_-- > wal->list) {
GEM_BUG_ON(i915_mmio_reg_offset(wa_[0].reg) ==
i915_mmio_reg_offset(wa_[1].reg));
Annotation
- Immediate include surface: `drm/intel/intel_gmd_misc_regs.h`, `i915_drv.h`, `i915_reg.h`, `i915_mmio_range.h`, `intel_context.h`, `intel_engine_pm.h`, `intel_engine_regs.h`, `intel_gpu_commands.h`.
- Detected declarations: `function xcs_engine_wa_init`, `function wa_init_finish`, `function wal_get_fw_for_rmw`, `function _wa_add`, `function wa_add`, `function wa_mcr_add`, `function wa_write_clr_set`, `function wa_mcr_write_clr_set`, `function wa_write`, `function wa_write_or`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.