drivers/gpu/drm/i915/gt/intel_workarounds_types.h

File Facts

System

Linux kernel

Corpus path

drivers/gpu/drm/i915/gt/intel_workarounds_types.h

Extension

.h

Size

589 bytes

Lines

38

Domain

Driver Families

Bucket

drivers/gpu

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• linux/types.h
• i915_reg_defs.h

Detected Declarations

• struct intel_gt
• struct i915_wa
• struct i915_wa_list

Annotated Snippet

struct i915_wa {
	union {
		i915_reg_t	reg;
		i915_mcr_reg_t	mcr_reg;
	};
	u32		clr;
	u32		set;
	u32		read;

	u32		masked_reg:1;
	u32		is_mcr:1;
};

struct i915_wa_list {
	struct intel_gt	*gt;
	const char	*name;
	const char	*engine_name;
	struct i915_wa	*list;
	unsigned int	count;
	unsigned int	wa_count;
};

#endif /* __INTEL_WORKAROUNDS_TYPES_H__ */

Annotation

• Immediate include surface: `linux/types.h`, `i915_reg_defs.h`.
• Detected declarations: `struct intel_gt`, `struct i915_wa`, `struct i915_wa_list`.
• Atlas domain: Driver Families / drivers/gpu.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.