drivers/gpu/drm/i915/gt/selftest_engine_cs.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/i915/gt/selftest_engine_cs.c- Extension
.c- Size
- 8673 bytes
- Lines
- 444
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/sort.hintel_gpu_commands.hintel_gt_pm.hintel_rps.hi915_selftest.hselftests/igt_flush_test.h
Detected Declarations
function cmp_u32function perf_beginfunction perf_endfunction timestamp_regfunction write_timestampfunction trifilterfunction perf_mi_bb_startfunction perf_mi_noopfunction intel_engine_cs_perf_selftestsfunction intel_mmio_bases_checkfunction intel_engine_cs_mock_selftests
Annotated Snippet
if (IS_ERR(batch)) {
err = PTR_ERR(batch);
intel_engine_pm_put(engine);
break;
}
err = i915_vma_sync(batch);
if (err) {
intel_engine_pm_put(engine);
i915_vma_put(batch);
break;
}
for (i = 0; i < ARRAY_SIZE(cycles); i++) {
struct i915_request *rq;
rq = i915_request_create(ce);
if (IS_ERR(rq)) {
err = PTR_ERR(rq);
break;
}
err = write_timestamp(rq, 2);
if (err)
goto out;
err = rq->engine->emit_bb_start(rq,
i915_vma_offset(batch), 8,
0);
if (err)
goto out;
err = write_timestamp(rq, 3);
if (err)
goto out;
out:
i915_request_get(rq);
i915_request_add(rq);
if (i915_request_wait(rq, 0, HZ / 5) < 0)
err = -EIO;
i915_request_put(rq);
if (err)
break;
cycles[i] = rq->hwsp_seqno[3] - rq->hwsp_seqno[2];
}
i915_vma_put(batch);
intel_engine_pm_put(engine);
if (err)
break;
pr_info("%s: MI_BB_START cycles: %u\n",
engine->name, trifilter(cycles));
}
if (perf_end(gt, wakeref))
err = -EIO;
return err;
}
static struct i915_vma *create_nop_batch(struct intel_context *ce)
{
struct drm_i915_gem_object *obj;
struct i915_vma *vma;
u32 *cs;
int err;
obj = i915_gem_object_create_internal(ce->engine->i915, SZ_64K);
if (IS_ERR(obj))
return ERR_CAST(obj);
cs = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WB);
if (IS_ERR(cs)) {
err = PTR_ERR(cs);
goto err_put;
}
memset(cs, 0, SZ_64K);
cs[SZ_64K / sizeof(*cs) - 1] = MI_BATCH_BUFFER_END;
i915_gem_object_flush_map(obj);
vma = i915_vma_instance(obj, ce->vm, NULL);
if (IS_ERR(vma)) {
err = PTR_ERR(vma);
goto err_unpin;
}
Annotation
- Immediate include surface: `linux/sort.h`, `intel_gpu_commands.h`, `intel_gt_pm.h`, `intel_rps.h`, `i915_selftest.h`, `selftests/igt_flush_test.h`.
- Detected declarations: `function cmp_u32`, `function perf_begin`, `function perf_end`, `function timestamp_reg`, `function write_timestamp`, `function trifilter`, `function perf_mi_bb_start`, `function perf_mi_noop`, `function intel_engine_cs_perf_selftests`, `function intel_mmio_bases_check`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.