drivers/gpu/drm/i915/gt/selftest_mocs.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/i915/gt/selftest_mocs.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/i915/gt/selftest_mocs.c- Extension
.c- Size
- 9529 bytes
- Lines
- 454
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
gt/intel_engine_pm.hgt/intel_gpu_commands.hi915_selftest.hgem/selftests/igt_gem_utils.hgem/selftests/mock_context.hselftests/igt_reset.hselftests/igt_spinner.hselftests/intel_scheduler_helpers.h
Detected Declarations
struct live_mocsfunction request_add_syncfunction request_add_spinfunction live_mocs_initfunction live_mocs_finifunction read_regsfunction read_mocs_tablefunction read_l3cc_tablefunction check_mocs_tablefunction for_each_mocsfunction mcr_rangefunction check_l3cc_tablefunction for_each_l3ccfunction check_mocs_enginefunction live_mocs_kernelfunction for_each_enginefunction live_mocs_cleanfunction for_each_enginefunction active_engine_resetfunction __live_mocs_resetfunction live_mocs_resetfunction intel_mocs_live_selftests
Annotated Snippet
struct live_mocs {
struct drm_i915_mocs_table table;
struct drm_i915_mocs_table *mocs;
struct drm_i915_mocs_table *l3cc;
struct i915_vma *scratch;
void *vaddr;
};
static struct intel_context *mocs_context_create(struct intel_engine_cs *engine)
{
struct intel_context *ce;
ce = intel_context_create(engine);
if (IS_ERR(ce))
return ce;
/* We build large requests to read the registers from the ring */
ce->ring_size = SZ_16K;
return ce;
}
static int request_add_sync(struct i915_request *rq, int err)
{
i915_request_get(rq);
i915_request_add(rq);
if (i915_request_wait(rq, 0, HZ / 5) < 0)
err = -ETIME;
i915_request_put(rq);
return err;
}
static int request_add_spin(struct i915_request *rq, struct igt_spinner *spin)
{
int err = 0;
i915_request_get(rq);
i915_request_add(rq);
if (spin && !igt_wait_for_spinner(spin, rq))
err = -ETIME;
i915_request_put(rq);
return err;
}
static int live_mocs_init(struct live_mocs *arg, struct intel_gt *gt)
{
unsigned int flags;
int err;
memset(arg, 0, sizeof(*arg));
flags = get_mocs_settings(gt->i915, &arg->table);
if (!flags)
return -EINVAL;
if (flags & HAS_RENDER_L3CC)
arg->l3cc = &arg->table;
if (flags & (HAS_GLOBAL_MOCS | HAS_ENGINE_MOCS))
arg->mocs = &arg->table;
arg->scratch =
__vm_create_scratch_for_read_pinned(>->ggtt->vm, PAGE_SIZE);
if (IS_ERR(arg->scratch))
return PTR_ERR(arg->scratch);
arg->vaddr = i915_gem_object_pin_map_unlocked(arg->scratch->obj, I915_MAP_WB);
if (IS_ERR(arg->vaddr)) {
err = PTR_ERR(arg->vaddr);
goto err_scratch;
}
return 0;
err_scratch:
i915_vma_unpin_and_release(&arg->scratch, 0);
return err;
}
static void live_mocs_fini(struct live_mocs *arg)
{
i915_vma_unpin_and_release(&arg->scratch, I915_VMA_RELEASE_MAP);
}
static int read_regs(struct i915_request *rq,
u32 addr, unsigned int count,
u32 *offset)
{
Annotation
- Immediate include surface: `gt/intel_engine_pm.h`, `gt/intel_gpu_commands.h`, `i915_selftest.h`, `gem/selftests/igt_gem_utils.h`, `gem/selftests/mock_context.h`, `selftests/igt_reset.h`, `selftests/igt_spinner.h`, `selftests/intel_scheduler_helpers.h`.
- Detected declarations: `struct live_mocs`, `function request_add_sync`, `function request_add_spin`, `function live_mocs_init`, `function live_mocs_fini`, `function read_regs`, `function read_mocs_table`, `function read_l3cc_table`, `function check_mocs_table`, `function for_each_mocs`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.