drivers/gpu/drm/i915/gt/shaders/clear_kernel/ivb.asm

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/i915/gt/shaders/clear_kernel/ivb.asm

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/i915/gt/shaders/clear_kernel/ivb.asm
Extension
.asm
Size
6973 bytes
Lines
118
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: drivers/gpu
Status
atlas-only

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: MIT
/*
 * Copyright © 2020 Intel Corporation
 */

/*
 * Kernel for PAVP buffer clear.
 *
 *	1. Clear all 64 GRF registers assigned to the kernel with designated value;
 *	2. Write 32x16 block of all "0" to render target buffer which indirectly clears
 *	   512 bytes of Render Cache.
 */

/* Store designated "clear GRF" value */
mov(1)          f0.1<1>UW       g1.2<0,1,0>UW                   { align1 1N };

/**
 * Curbe Format
 *
 * DW 1.0 - Block Offset to write Render Cache
 * DW 1.1 [15:0] - Clear Word
 * DW 1.2 - Delay iterations
 * DW 1.3 - Enable Instrumentation (only for debug)
 * DW 1.4 - Rsvd (intended for context ID)
 * DW 1.5 - [31:16]:SliceCount, [15:0]:SubSlicePerSliceCount
 * DW 1.6 - Rsvd MBZ (intended for Enable Wait on Total Thread Count)
 * DW 1.7 - Rsvd MBZ (intended for Total Thread Count)
 *
 * Binding Table
 *
 * BTI 0: 2D Surface to help clear L3 (Render/Data Cache)
 * BTI 1: Wait/Instrumentation Buffer
 *  Size : (SliceCount * SubSliceCount  * 16 EUs/SubSlice) rows * (16 threads/EU) cols (Format R32_UINT)
 *         Expected to be initialized to 0 by driver/another kernel
 *  Layout :
 *           RowN: Histogram for EU-N: (SliceID*SubSlicePerSliceCount + SSID)*16 + EUID [assume max 16 EUs / SS]
 *           Col-k[DW-k]: Threads Executed on ThreadID-k for EU-N
 */
add(1)          g1.2<1>UD       g1.2<0,1,0>UD   0x00000001UD    { align1 1N }; /* Loop count to delay kernel: Init to (g1.2 + 1) */
cmp.z.f0.0(1)   null<1>UD       g1.3<0,1,0>UD   0x00000000UD    { align1 1N };
(+f0.0) jmpi(1) 44D                                             { align1 WE_all 1N };

/**
 * State Register has info on where this thread is running
 *	IVB: sr0.0 :: [15:13]: MBZ, 12: HSID (Half-Slice ID), [11:8]EUID, [2:0] ThreadSlotID
 *	HSW: sr0.0 :: 15: MBZ, [14:13]: SliceID, 12: HSID (Half-Slice ID), [11:8]EUID, [2:0] ThreadSlotID
 */
mov(8)          g3<1>UD         0x00000000UD                    { align1 1Q };
shr(1)          g3<1>D          sr0<0,1,0>D     12D             { align1 1N };
and(1)          g3<1>D          g3<0,1,0>D      1D              { align1 1N }; /* g3 has HSID */
shr(1)          g3.1<1>D        sr0<0,1,0>D     13D             { align1 1N };
and(1)          g3.1<1>D        g3.1<0,1,0>D    3D              { align1 1N }; /* g3.1 has sliceID */
mul(1)          g3.5<1>D        g3.1<0,1,0>D    g1.10<0,1,0>UW  { align1 1N };
add(1)          g3<1>D          g3<0,1,0>D      g3.5<0,1,0>D    { align1 1N }; /* g3 = sliceID * SubSlicePerSliceCount + HSID */
shr(1)          g3.2<1>D        sr0<0,1,0>D     8D              { align1 1N };
and(1)          g3.2<1>D        g3.2<0,1,0>D    15D             { align1 1N }; /* g3.2 = EUID */
mul(1)          g3.4<1>D        g3<0,1,0>D      16D             { align1 1N };
add(1)          g3.2<1>D        g3.2<0,1,0>D    g3.4<0,1,0>D    { align1 1N }; /* g3.2 now points to EU row number (Y-pixel = V address )  in instrumentation surf */

mov(8)          g5<1>UD         0x00000000UD                    { align1 1Q };
and(1)          g3.3<1>D        sr0<0,1,0>D     7D              { align1 1N };
mul(1)          g3.3<1>D        g3.3<0,1,0>D    4D              { align1 1N };

mov(8)          g4<1>UD         g0<8,8,1>UD                     { align1 1Q }; /* Initialize message header with g0 */
mov(1)          g4<1>UD         g3.3<0,1,0>UD                   { align1 1N }; /* Block offset */
mov(1)          g4.1<1>UD       g3.2<0,1,0>UD                   { align1 1N }; /* Block offset */
mov(1)          g4.2<1>UD       0x00000003UD                    { align1 1N }; /* Block size (1 row x 4 bytes) */
and(1)          g4.3<1>UD       g4.3<0,1,0>UW   0xffffffffUD    { align1 1N };

/* Media block read to fetch current value at specified location in instrumentation buffer */

Annotation

Implementation Notes