drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
Extension
.c
Size
38526 bytes
Lines
1400
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct ct_request {
	struct list_head link;
	u32 fence;
	u32 status;
	u32 response_len;
	u32 *response_buf;
};

struct ct_incoming_msg {
	struct list_head link;
	u32 size;
	u32 msg[] __counted_by(size);
};

enum { CTB_SEND = 0, CTB_RECV = 1 };

enum { CTB_OWNER_HOST = 0 };

/*
 * Some H2G commands involve a synchronous response that the driver needs
 * to wait for. In such cases, a timeout is required to prevent the driver
 * from waiting forever in the case of an error (either no error response
 * is defined in the protocol or something has died and requires a reset).
 * The specific command may be defined as having a time bound response but
 * the CT is a queue and that time guarantee only starts from the point
 * when the command reaches the head of the queue and is processed by GuC.
 *
 * Ideally there would be a helper to report the progress of a given
 * command through the CT. However, that would require a significant
 * amount of work in the CT layer. In the meantime, provide a reasonable
 * estimation of the worst case latency it should take for the entire
 * queue to drain. And therefore, how long a caller should wait before
 * giving up on their request. The current estimate is based on empirical
 * measurement of a test that fills the buffer with context creation and
 * destruction requests as they seem to be the slowest operation.
 */
long intel_guc_ct_max_queue_time_jiffies(void)
{
	/*
	 * A 4KB buffer full of context destroy commands takes a little
	 * over a second to process so bump that to 2s to be super safe.
	 */
	return (CTB_H2G_BUFFER_SIZE * HZ) / SZ_2K;
}

static void ct_receive_tasklet_func(struct tasklet_struct *t);
static void ct_incoming_request_worker_func(struct work_struct *w);

/**
 * intel_guc_ct_init_early - Initialize CT state without requiring device access
 * @ct: pointer to CT struct
 */
void intel_guc_ct_init_early(struct intel_guc_ct *ct)
{
	spin_lock_init(&ct->ctbs.send.lock);
	spin_lock_init(&ct->ctbs.recv.lock);
	spin_lock_init(&ct->requests.lock);
	INIT_LIST_HEAD(&ct->requests.pending);
	INIT_LIST_HEAD(&ct->requests.incoming);
#if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
	INIT_WORK(&ct->dead_ct_worker, ct_dead_ct_worker_func);
#endif
	INIT_WORK(&ct->requests.worker, ct_incoming_request_worker_func);
	tasklet_setup(&ct->receive_tasklet, ct_receive_tasklet_func);
	init_waitqueue_head(&ct->wq);
}

static void guc_ct_buffer_desc_init(struct guc_ct_buffer_desc *desc)
{
	memset(desc, 0, sizeof(*desc));
}

static void guc_ct_buffer_reset(struct intel_guc_ct_buffer *ctb)
{
	u32 space;

	ctb->broken = false;
	ctb->tail = 0;
	ctb->head = 0;
	space = CIRC_SPACE(ctb->tail, ctb->head, ctb->size) - ctb->resv_space;
	atomic_set(&ctb->space, space);

	guc_ct_buffer_desc_init(ctb->desc);
}

static void guc_ct_buffer_init(struct intel_guc_ct_buffer *ctb,
			       struct guc_ct_buffer_desc *desc,
			       u32 *cmds, u32 size_in_bytes, u32 resv_space)
{
	GEM_BUG_ON(size_in_bytes % 4);

Annotation

Implementation Notes