drivers/gpu/drm/i915/gt/uc/intel_guc.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/i915/gt/uc/intel_guc.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/i915/gt/uc/intel_guc.h- Extension
.h- Size
- 16839 bytes
- Lines
- 555
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/delay.hlinux/iosys-map.hlinux/xarray.hintel_guc_ct.hintel_guc_fw.hintel_guc_fwif.hintel_guc_log.hintel_guc_reg.hintel_guc_slpc_types.hintel_uc_fw.hintel_uncore.hi915_utils.hi915_vma.h
Detected Declarations
struct __guc_ads_blobstruct intel_guc_state_capturestruct intel_gucstruct intel_guc_tlb_waitfunction intel_guc_sendfunction intel_guc_send_nbfunction intel_guc_send_and_receivefunction intel_guc_send_busy_loopfunction intel_guc_to_host_event_handlerfunction intel_guc_ggtt_offsetfunction intel_guc_is_supportedfunction intel_guc_is_wantedfunction intel_guc_is_usedfunction intel_guc_is_fw_runningfunction intel_guc_is_readyfunction intel_guc_reset_interruptsfunction intel_guc_enable_interruptsfunction intel_guc_disable_interruptsfunction intel_guc_sanitizefunction intel_guc_enable_msgfunction intel_guc_disable_msg
Annotated Snippet
struct intel_guc {
/** @fw: the GuC firmware */
struct intel_uc_fw fw;
/** @log: sub-structure containing GuC log related data and objects */
struct intel_guc_log log;
/** @ct: the command transport communication channel */
struct intel_guc_ct ct;
/** @slpc: sub-structure containing SLPC related data and objects */
struct intel_guc_slpc slpc;
/** @capture: the error-state-capture module's data and objects */
struct intel_guc_state_capture *capture;
/** @dbgfs_node: debugfs node */
struct dentry *dbgfs_node;
/** @sched_engine: Global engine used to submit requests to GuC */
struct i915_sched_engine *sched_engine;
/**
* @stalled_request: if GuC can't process a request for any reason, we
* save it until GuC restarts processing. No other request can be
* submitted until the stalled request is processed.
*/
struct i915_request *stalled_request;
/**
* @submission_stall_reason: reason why submission is stalled
*/
enum {
STALL_NONE,
STALL_REGISTER_CONTEXT,
STALL_MOVE_LRC_TAIL,
STALL_ADD_REQUEST,
} submission_stall_reason;
/* intel_guc_recv interrupt related state */
/** @irq_lock: protects GuC irq state */
spinlock_t irq_lock;
/**
* @msg_enabled_mask: mask of events that are processed when receiving
* an INTEL_GUC_ACTION_DEFAULT G2H message.
*/
unsigned int msg_enabled_mask;
/**
* @outstanding_submission_g2h: number of outstanding GuC to Host
* responses related to GuC submission, used to determine if the GT is
* idle
*/
atomic_t outstanding_submission_g2h;
/** @tlb_lookup: xarray to store all pending TLB invalidation requests */
struct xarray tlb_lookup;
/**
* @serial_slot: id to the initial waiter created in tlb_lookup,
* which is used only when failed to allocate new waiter.
*/
u32 serial_slot;
/** @next_seqno: the next id (sequence number) to allocate. */
u32 next_seqno;
/** @interrupts: pointers to GuC interrupt-managing functions. */
struct {
bool enabled;
void (*reset)(struct intel_guc *guc);
void (*enable)(struct intel_guc *guc);
void (*disable)(struct intel_guc *guc);
} interrupts;
/**
* @submission_state: sub-structure for submission state protected by
* single lock
*/
struct {
/**
* @submission_state.lock: protects everything in
* submission_state, ce->guc_id.id, and ce->guc_id.ref
* when transitioning in and out of zero
*/
spinlock_t lock;
/**
* @submission_state.guc_ids: used to allocate new
* guc_ids, single-lrc
*/
struct ida guc_ids;
/**
* @submission_state.num_guc_ids: Number of guc_ids, selftest
* feature to be able to reduce this number while testing.
*/
int num_guc_ids;
Annotation
- Immediate include surface: `linux/delay.h`, `linux/iosys-map.h`, `linux/xarray.h`, `intel_guc_ct.h`, `intel_guc_fw.h`, `intel_guc_fwif.h`, `intel_guc_log.h`, `intel_guc_reg.h`.
- Detected declarations: `struct __guc_ads_blob`, `struct intel_guc_state_capture`, `struct intel_guc`, `struct intel_guc_tlb_wait`, `function intel_guc_send`, `function intel_guc_send_nb`, `function intel_guc_send_and_receive`, `function intel_guc_send_busy_loop`, `function intel_guc_to_host_event_handler`, `function intel_guc_ggtt_offset`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.