drivers/gpu/drm/i915/gvt/cmd_parser.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/i915/gvt/cmd_parser.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/i915/gvt/cmd_parser.c- Extension
.c- Size
- 97898 bytes
- Lines
- 3276
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/slab.hdrm/drm_print.hdrm/intel/intel_gmd_misc_regs.hdisplay/i9xx_plane_regs.hdisplay/intel_display_regs.hdisplay/intel_sprite_regs.hgem/i915_gem_context.hgem/i915_gem_pm.hgt/intel_context.hgt/intel_engine_regs.hgt/intel_gpu_commands.hgt/intel_gt_regs.hgt/intel_gt_requests.hgt/intel_lrc.hgt/intel_ring.hgt/shmem_utils.hdisplay_helpers.hgvt.hi915_drv.hi915_pvinfo.hi915_reg.htrace.h
Detected Declarations
struct sub_op_bitsstruct decode_infostruct parser_exec_statestruct cmd_infostruct cmd_entrystruct parser_exec_statestruct cmd_interrupt_eventstruct mi_display_flip_command_infostruct plane_code_mappingfunction gvt_check_valid_cmd_lengthfunction get_opcodefunction find_cmd_entryfunction hash_for_each_possiblefunction get_cmd_infofunction sub_op_valfunction print_opcodefunction cmd_valfunction is_init_ctxfunction parser_exec_state_dumpfunction update_ip_vafunction ip_gma_setfunction ip_gma_advancefunction get_cmd_lengthfunction cmd_lengthfunction is_mocs_mmiofunction is_cmd_update_pdpsfunction cmd_pdp_mmio_update_handlerfunction cmd_reg_handlerfunction intel_gvt_mmio_is_sr_in_ctxfunction cmd_handler_lrifunction cmd_handler_lrrfunction cmd_handler_lrmfunction cmd_handler_srmfunction cmd_handler_pipe_controlfunction cmd_handler_mi_user_interruptfunction cmd_advance_defaultfunction cmd_handler_mi_batch_buffer_endfunction gen8_decode_mi_display_flipfunction skl_decode_mi_display_flipfunction gen8_check_mi_display_flipfunction gen8_update_plane_mmio_from_mi_display_flipfunction decode_mi_display_flipfunction check_mi_display_flipfunction update_plane_mmio_from_mi_display_flipfunction cmd_handler_mi_display_flipfunction is_wait_for_flip_pendingfunction cmd_handler_mi_wait_for_eventfunction get_gma_bb_from_cmd
Annotated Snippet
struct sub_op_bits {
int hi;
int low;
};
struct decode_info {
const char *name;
int op_len;
int nr_sub_op;
const struct sub_op_bits *sub_op;
};
#define MAX_CMD_BUDGET 0x7fffffff
#define MI_WAIT_FOR_PLANE_C_FLIP_PENDING (1<<15)
#define MI_WAIT_FOR_PLANE_B_FLIP_PENDING (1<<9)
#define MI_WAIT_FOR_PLANE_A_FLIP_PENDING (1<<1)
#define MI_WAIT_FOR_SPRITE_C_FLIP_PENDING (1<<20)
#define MI_WAIT_FOR_SPRITE_B_FLIP_PENDING (1<<10)
#define MI_WAIT_FOR_SPRITE_A_FLIP_PENDING (1<<2)
/* Render Command Map */
/* MI_* command Opcode (28:23) */
#define OP_MI_NOOP 0x0
#define OP_MI_SET_PREDICATE 0x1 /* HSW+ */
#define OP_MI_USER_INTERRUPT 0x2
#define OP_MI_WAIT_FOR_EVENT 0x3
#define OP_MI_FLUSH 0x4
#define OP_MI_ARB_CHECK 0x5
#define OP_MI_RS_CONTROL 0x6 /* HSW+ */
#define OP_MI_REPORT_HEAD 0x7
#define OP_MI_ARB_ON_OFF 0x8
#define OP_MI_URB_ATOMIC_ALLOC 0x9 /* HSW+ */
#define OP_MI_BATCH_BUFFER_END 0xA
#define OP_MI_SUSPEND_FLUSH 0xB
#define OP_MI_PREDICATE 0xC /* IVB+ */
#define OP_MI_TOPOLOGY_FILTER 0xD /* IVB+ */
#define OP_MI_SET_APPID 0xE /* IVB+ */
#define OP_MI_RS_CONTEXT 0xF /* HSW+ */
#define OP_MI_LOAD_SCAN_LINES_INCL 0x12 /* HSW+ */
#define OP_MI_DISPLAY_FLIP 0x14
#define OP_MI_SEMAPHORE_MBOX 0x16
#define OP_MI_SET_CONTEXT 0x18
#define OP_MI_MATH 0x1A
#define OP_MI_URB_CLEAR 0x19
#define OP_MI_SEMAPHORE_SIGNAL 0x1B /* BDW+ */
#define OP_MI_SEMAPHORE_WAIT 0x1C /* BDW+ */
#define OP_MI_STORE_DATA_IMM 0x20
#define OP_MI_STORE_DATA_INDEX 0x21
#define OP_MI_LOAD_REGISTER_IMM 0x22
#define OP_MI_UPDATE_GTT 0x23
#define OP_MI_STORE_REGISTER_MEM 0x24
#define OP_MI_FLUSH_DW 0x26
#define OP_MI_CLFLUSH 0x27
#define OP_MI_REPORT_PERF_COUNT 0x28
#define OP_MI_LOAD_REGISTER_MEM 0x29 /* HSW+ */
#define OP_MI_LOAD_REGISTER_REG 0x2A /* HSW+ */
#define OP_MI_RS_STORE_DATA_IMM 0x2B /* HSW+ */
#define OP_MI_LOAD_URB_MEM 0x2C /* HSW+ */
#define OP_MI_STORE_URM_MEM 0x2D /* HSW+ */
#define OP_MI_2E 0x2E /* BDW+ */
#define OP_MI_2F 0x2F /* BDW+ */
#define OP_MI_BATCH_BUFFER_START 0x31
/* Bit definition for dword 0 */
#define _CMDBIT_BB_START_IN_PPGTT (1UL << 8)
#define OP_MI_CONDITIONAL_BATCH_BUFFER_END 0x36
#define BATCH_BUFFER_ADDR_MASK ((1UL << 32) - (1U << 2))
#define BATCH_BUFFER_ADDR_HIGH_MASK ((1UL << 16) - (1U))
#define BATCH_BUFFER_ADR_SPACE_BIT(x) (((x) >> 8) & 1U)
#define BATCH_BUFFER_2ND_LEVEL_BIT(x) ((x) >> 22 & 1U)
/* 2D command: Opcode (28:22) */
#define OP_2D(x) ((2<<7) | x)
#define OP_XY_SETUP_BLT OP_2D(0x1)
#define OP_XY_SETUP_CLIP_BLT OP_2D(0x3)
#define OP_XY_SETUP_MONO_PATTERN_SL_BLT OP_2D(0x11)
#define OP_XY_PIXEL_BLT OP_2D(0x24)
#define OP_XY_SCANLINES_BLT OP_2D(0x25)
#define OP_XY_TEXT_BLT OP_2D(0x26)
#define OP_XY_TEXT_IMMEDIATE_BLT OP_2D(0x31)
#define OP_XY_COLOR_BLT OP_2D(0x50)
#define OP_XY_PAT_BLT OP_2D(0x51)
#define OP_XY_MONO_PAT_BLT OP_2D(0x52)
#define OP_XY_SRC_COPY_BLT OP_2D(0x53)
#define OP_XY_MONO_SRC_COPY_BLT OP_2D(0x54)
Annotation
- Immediate include surface: `linux/slab.h`, `drm/drm_print.h`, `drm/intel/intel_gmd_misc_regs.h`, `display/i9xx_plane_regs.h`, `display/intel_display_regs.h`, `display/intel_sprite_regs.h`, `gem/i915_gem_context.h`, `gem/i915_gem_pm.h`.
- Detected declarations: `struct sub_op_bits`, `struct decode_info`, `struct parser_exec_state`, `struct cmd_info`, `struct cmd_entry`, `struct parser_exec_state`, `struct cmd_interrupt_event`, `struct mi_display_flip_command_info`, `struct plane_code_mapping`, `function gvt_check_valid_cmd_length`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.