drivers/gpu/drm/i915/gvt/edid.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/i915/gvt/edid.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/i915/gvt/edid.h
Extension
.h
Size
4000 bytes
Lines
147
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct intel_vgpu_edid_data {
	bool data_valid;
	unsigned char edid_block[EDID_SIZE];
};

enum gmbus_cycle_type {
	GMBUS_NOCYCLE	= 0x0,
	NIDX_NS_W	= 0x1,
	IDX_NS_W	= 0x3,
	GMBUS_STOP	= 0x4,
	NIDX_STOP	= 0x5,
	IDX_STOP	= 0x7
};

/*
 * States of GMBUS
 *
 * GMBUS0-3 could be related to the EDID virtualization. Another two GMBUS
 * registers, GMBUS4 (interrupt mask) and GMBUS5 (2 byte indes register), are
 * not considered here. Below describes the usage of GMBUS registers that are
 * cared by the EDID virtualization
 *
 * GMBUS0:
 *      R/W
 *      port selection. value of bit0 - bit2 corresponds to the GPIO registers.
 *
 * GMBUS1:
 *      R/W Protect
 *      Command and Status.
 *      bit0 is the direction bit: 1 is read; 0 is write.
 *      bit1 - bit7 is target 7-bit address.
 *      bit16 - bit24 total byte count (ignore?)
 *
 * GMBUS2:
 *      Most of bits are read only except bit 15 (IN_USE)
 *      Status register
 *      bit0 - bit8 current byte count
 *      bit 11: hardware ready;
 *
 * GMBUS3:
 *      Read/Write
 *      Data for transfer
 */

/* From hw specs, Other phases like START, ADDRESS, INDEX
 * are invisible to GMBUS MMIO interface. So no definitions
 * in below enum types
 */
enum gvt_gmbus_phase {
	GMBUS_IDLE_PHASE = 0,
	GMBUS_DATA_PHASE,
	GMBUS_WAIT_PHASE,
	//GMBUS_STOP_PHASE,
	GMBUS_MAX_PHASE
};

struct intel_vgpu_i2c_gmbus {
	unsigned int total_byte_count; /* from GMBUS1 */
	enum gmbus_cycle_type cycle_type;
	enum gvt_gmbus_phase phase;
};

struct intel_vgpu_i2c_aux_ch {
	bool i2c_over_aux_ch;
	bool aux_ch_mot;
};

enum i2c_state {
	I2C_NOT_SPECIFIED = 0,
	I2C_GMBUS = 1,
	I2C_AUX_CH = 2
};

/* I2C sequences cannot interleave.
 * GMBUS and AUX_CH sequences cannot interleave.
 */
struct intel_vgpu_i2c_edid {
	enum i2c_state state;

	unsigned int port;
	bool target_selected;
	bool edid_available;
	unsigned int current_edid_read;

	struct intel_vgpu_i2c_gmbus gmbus;
	struct intel_vgpu_i2c_aux_ch aux_ch;
};

void intel_vgpu_init_i2c_edid(struct intel_vgpu *vgpu);

Annotation

Implementation Notes