drivers/gpu/drm/i915/gvt/handlers.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/i915/gvt/handlers.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/i915/gvt/handlers.c
Extension
.c
Size
98654 bytes
Lines
3256
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (!p) {
			WARN(1, "assign a handler to a non-tracked mmio %x\n",
				i);
			return -ENODEV;
		}
		p->ro_mask = ro_mask;
		gvt->mmio.mmio_attribute[i / 4] = flags;
		if (read)
			p->read = read;
		if (write)
			p->write = write;
	}
	return 0;
}

/**
 * intel_gvt_render_mmio_to_engine - convert a mmio offset into the engine
 * @gvt: a GVT device
 * @offset: register offset
 *
 * Returns:
 * The engine containing the offset within its mmio page.
 */
const struct intel_engine_cs *
intel_gvt_render_mmio_to_engine(struct intel_gvt *gvt, unsigned int offset)
{
	struct intel_engine_cs *engine;
	enum intel_engine_id id;

	offset &= ~GENMASK(11, 0);
	for_each_engine(engine, gvt->gt, id)
		if (engine->mmio_base == offset)
			return engine;

	return NULL;
}

#define offset_to_fence_num(offset) \
	((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3)

#define fence_num_to_offset(num) \
	(num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0)))


void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason)
{
	switch (reason) {
	case GVT_FAILSAFE_UNSUPPORTED_GUEST:
		pr_err("Detected your guest driver doesn't support GVT-g.\n");
		break;
	case GVT_FAILSAFE_INSUFFICIENT_RESOURCE:
		pr_err("Graphics resource is not enough for the guest\n");
		break;
	case GVT_FAILSAFE_GUEST_ERR:
		pr_err("GVT Internal error  for the guest\n");
		break;
	default:
		break;
	}
	pr_err("Now vgpu %d will enter failsafe mode.\n", vgpu->id);
	vgpu->failsafe = true;
}

static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu,
		unsigned int fence_num, void *p_data, unsigned int bytes)
{
	unsigned int max_fence = vgpu_fence_sz(vgpu);

	if (fence_num >= max_fence) {
		gvt_vgpu_err("access oob fence reg %d/%d\n",
			     fence_num, max_fence);

		/* When guest access oob fence regs without access
		 * pv_info first, we treat guest not supporting GVT,
		 * and we will let vgpu enter failsafe mode.
		 */
		if (!vgpu->pv_notified)
			enter_failsafe_mode(vgpu,
					GVT_FAILSAFE_UNSUPPORTED_GUEST);

		memset(p_data, 0, bytes);
		return -EINVAL;
	}
	return 0;
}

static int gamw_echo_dev_rw_ia_write(struct intel_vgpu *vgpu,
		unsigned int offset, void *p_data, unsigned int bytes)
{
	u32 ips = (*(u32 *)p_data) & GAMW_ECO_ENABLE_64K_IPS_FIELD;

Annotation

Implementation Notes