drivers/gpu/drm/i915/gvt/reg.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/i915/gvt/reg.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/i915/gvt/reg.h
Extension
.h
Size
5268 bytes
Lines
142
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _GVT_REG_H
#define _GVT_REG_H

#define INTEL_GVT_PCI_CLASS_VGA_OTHER   0x80

#define INTEL_GVT_PCI_GMCH_CONTROL	0x50
#define   BDW_GMCH_GMS_SHIFT		8
#define   BDW_GMCH_GMS_MASK		0xff

#define INTEL_GVT_PCI_SWSCI		0xe8
#define   SWSCI_SCI_SELECT		(1 << 15)
#define   SWSCI_SCI_TRIGGER		1

#define INTEL_GVT_PCI_OPREGION		0xfc

#define INTEL_GVT_OPREGION_CLID		0x1AC
#define INTEL_GVT_OPREGION_SCIC		0x200
#define   OPREGION_SCIC_FUNC_MASK	0x1E
#define   OPREGION_SCIC_FUNC_SHIFT	1
#define   OPREGION_SCIC_SUBFUNC_MASK	0xFF00
#define   OPREGION_SCIC_SUBFUNC_SHIFT	8
#define   OPREGION_SCIC_EXIT_MASK	0xE0
#define INTEL_GVT_OPREGION_SCIC_F_GETBIOSDATA         4
#define INTEL_GVT_OPREGION_SCIC_F_GETBIOSCALLBACKS    6
#define INTEL_GVT_OPREGION_SCIC_SF_SUPPRTEDCALLS      0
#define INTEL_GVT_OPREGION_SCIC_SF_REQEUSTEDCALLBACKS 1
#define INTEL_GVT_OPREGION_PARM                   0x204

#define INTEL_GVT_OPREGION_PAGES	2
#define INTEL_GVT_OPREGION_SIZE		(INTEL_GVT_OPREGION_PAGES * PAGE_SIZE)
#define INTEL_GVT_OPREGION_VBT_OFFSET	0x400
#define INTEL_GVT_OPREGION_VBT_SIZE	\
		(INTEL_GVT_OPREGION_SIZE - INTEL_GVT_OPREGION_VBT_OFFSET)

#define VGT_SPRSTRIDE(pipe)	_PIPE(pipe, _SPRA_STRIDE, _PLANE_STRIDE_2_B)

#define SKL_FLIP_EVENT(pipe, plane) (PRIMARY_A_FLIP_DONE + (plane) * 3 + (pipe))

#define REG50080_FLIP_TYPE_MASK	0x3
#define REG50080_FLIP_TYPE_ASYNC	0x1

#define REG_50080(_pipe, _plane) ({ \
	typeof(_pipe) (p) = (_pipe); \
	typeof(_plane) (q) = (_plane); \
	(((p) == PIPE_A) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50080)) : \
		(_MMIO(0x50090))) : \
	(((p) == PIPE_B) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50088)) : \
		(_MMIO(0x50098))) : \
	(((p) == PIPE_C) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x5008C)) : \
		(_MMIO(0x5009C))) : \
		(_MMIO(0x50080))))); })

#define REG_50080_TO_PIPE(_reg) ({ \
	typeof(_reg) (reg) = (_reg); \
	(((reg) == 0x50080 || (reg) == 0x50090) ? (PIPE_A) : \
	(((reg) == 0x50088 || (reg) == 0x50098) ? (PIPE_B) : \
	(((reg) == 0x5008C || (reg) == 0x5009C) ? (PIPE_C) : \
	(INVALID_PIPE)))); })

#define REG_50080_TO_PLANE(_reg) ({ \
	typeof(_reg) (reg) = (_reg); \
	(((reg) == 0x50080 || (reg) == 0x50088 || (reg) == 0x5008C) ? \
		(PLANE_PRIMARY) : \
	(((reg) == 0x50090 || (reg) == 0x50098 || (reg) == 0x5009C) ? \
		(PLANE_SPRITE0) : (I915_MAX_PLANES))); })

#define GFX_MODE_BIT_SET_IN_MASK(val, bit) \
		((((bit) & 0xffff0000) == 0) && !!((val) & (((bit) << 16))))

#define IS_MASKED_BITS_ENABLED(_val, _b) \
		(((_val) & REG_MASKED_FIELD_ENABLE(_b)) == REG_MASKED_FIELD_ENABLE(_b))
#define IS_MASKED_BITS_DISABLED(_val, _b) \
		((_val) & REG_MASKED_FIELD_DISABLE(_b))

#define FORCEWAKE_RENDER_GEN9_REG 0xa278
#define FORCEWAKE_ACK_RENDER_GEN9_REG 0x0D84
#define FORCEWAKE_GT_GEN9_REG 0xa188
#define FORCEWAKE_ACK_GT_GEN9_REG 0x130044
#define FORCEWAKE_MEDIA_GEN9_REG 0xa270
#define FORCEWAKE_ACK_MEDIA_GEN9_REG 0x0D88
#define FORCEWAKE_ACK_HSW_REG 0x130044

#define RB_HEAD_WRAP_CNT_MAX	((1 << 11) - 1)
#define RB_HEAD_WRAP_CNT_OFF	21
#define RB_HEAD_OFF_MASK	((1U << 21) - (1U << 2))
#define RB_TAIL_OFF_MASK	((1U << 21) - (1U << 3))
#define RB_TAIL_SIZE_MASK	((1U << 21) - (1U << 12))
#define _RING_CTL_BUF_SIZE(ctl) (((ctl) & RB_TAIL_SIZE_MASK) + \
		I915_GTT_PAGE_SIZE)

Annotation

Implementation Notes