drivers/gpu/drm/i915/gvt/scheduler.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/i915/gvt/scheduler.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/i915/gvt/scheduler.c- Extension
.c- Size
- 49755 bytes
- Lines
- 1796
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/kthread.hdrm/drm_print.hgem/i915_gem_pm.hgt/intel_context.hgt/intel_engine_regs.hgt/intel_execlists_submission.hgt/intel_gt_regs.hgt/intel_lrc.hgt/intel_ring.hgvt.hi915_drv.hi915_gem_gtt.hi915_perf_oa_regs.hsched_policy.h
Detected Declarations
function Copyrightfunction update_shadow_pdpsfunction sr_oa_regsfunction populate_shadow_contextfunction is_gvt_requestfunction save_ring_hw_statefunction shadow_context_status_changefunction shadow_context_descriptor_updatefunction copy_workload_to_ring_bufferfunction release_shadow_wa_ctxfunction set_dma_addressfunction set_context_ppgtt_from_shadowfunction intel_gvt_workload_req_allocfunction intel_gvt_scan_and_shadow_workloadfunction prepare_shadow_batch_bufferfunction list_for_each_entryfunction update_wa_ctx_2_shadow_ctxfunction prepare_shadow_wa_ctxfunction update_vreg_in_ctxfunction release_shadow_batch_bufferfunction list_for_each_entry_safefunction intel_vgpu_shadow_mm_pinfunction intel_vgpu_shadow_mm_unpinfunction prepare_workloadfunction dispatch_workloadfunction pick_next_workloadfunction update_guest_pdpsfunction check_shadow_context_ppgttfunction update_guest_contextfunction intel_vgpu_clean_workloadsfunction list_for_each_entry_safefunction complete_current_workloadfunction workload_threadfunction intel_gvt_wait_vgpu_idlefunction intel_gvt_clean_workload_schedulerfunction for_each_enginefunction intel_gvt_init_workload_schedulerfunction for_each_enginefunction i915_context_ppgtt_root_restorefunction intel_vgpu_clean_submissionfunction intel_vgpu_reset_submissionfunction i915_context_ppgtt_root_savefunction intel_vgpu_setup_submissionfunction for_each_enginefunction intel_vgpu_select_submission_opsfunction intel_vgpu_destroy_workloadfunction list_for_each_entry_safefunction alloc_workload
Annotated Snippet
if (context_gpa == INTEL_GVT_INVALID_ADDR) {
gvt_vgpu_err("Invalid guest context descriptor\n");
return -EFAULT;
}
if (gpa_size == 0) {
gpa_base = context_gpa;
dst = context_base + (i << I915_GTT_PAGE_SHIFT);
} else if (context_gpa != gpa_base + gpa_size)
goto read;
gpa_size += I915_GTT_PAGE_SIZE;
if (i == context_page_num - 1)
goto read;
continue;
read:
intel_gvt_read_gpa(vgpu, gpa_base, dst, gpa_size);
gpa_base = context_gpa;
gpa_size = I915_GTT_PAGE_SIZE;
dst = context_base + (i << I915_GTT_PAGE_SHIFT);
}
ret = intel_gvt_scan_engine_context(workload);
if (ret) {
gvt_vgpu_err("invalid cmd found in guest context pages\n");
return ret;
}
s->last_ctx[ring_id].valid = true;
return 0;
}
static inline bool is_gvt_request(struct i915_request *rq)
{
return intel_context_force_single_submission(rq->context);
}
static void save_ring_hw_state(struct intel_vgpu *vgpu,
const struct intel_engine_cs *engine)
{
struct intel_uncore *uncore = engine->uncore;
i915_reg_t reg;
reg = RING_INSTDONE(engine->mmio_base);
vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) =
intel_uncore_read(uncore, reg);
reg = RING_ACTHD(engine->mmio_base);
vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) =
intel_uncore_read(uncore, reg);
reg = RING_ACTHD_UDW(engine->mmio_base);
vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) =
intel_uncore_read(uncore, reg);
}
static int shadow_context_status_change(struct notifier_block *nb,
unsigned long action, void *data)
{
struct i915_request *rq = data;
struct intel_gvt *gvt = container_of(nb, struct intel_gvt,
shadow_ctx_notifier_block[rq->engine->id]);
struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
enum intel_engine_id ring_id = rq->engine->id;
struct intel_vgpu_workload *workload;
unsigned long flags;
if (!is_gvt_request(rq)) {
spin_lock_irqsave(&scheduler->mmio_context_lock, flags);
if (action == INTEL_CONTEXT_SCHEDULE_IN &&
scheduler->engine_owner[ring_id]) {
/* Switch ring from vGPU to host. */
intel_gvt_switch_mmio(scheduler->engine_owner[ring_id],
NULL, rq->engine);
scheduler->engine_owner[ring_id] = NULL;
}
spin_unlock_irqrestore(&scheduler->mmio_context_lock, flags);
return NOTIFY_OK;
}
workload = scheduler->current_workload[ring_id];
if (unlikely(!workload))
return NOTIFY_OK;
switch (action) {
case INTEL_CONTEXT_SCHEDULE_IN:
spin_lock_irqsave(&scheduler->mmio_context_lock, flags);
if (workload->vgpu != scheduler->engine_owner[ring_id]) {
Annotation
- Immediate include surface: `linux/kthread.h`, `drm/drm_print.h`, `gem/i915_gem_pm.h`, `gt/intel_context.h`, `gt/intel_engine_regs.h`, `gt/intel_execlists_submission.h`, `gt/intel_gt_regs.h`, `gt/intel_lrc.h`.
- Detected declarations: `function Copyright`, `function update_shadow_pdps`, `function sr_oa_regs`, `function populate_shadow_context`, `function is_gvt_request`, `function save_ring_hw_state`, `function shadow_context_status_change`, `function shadow_context_descriptor_update`, `function copy_workload_to_ring_buffer`, `function release_shadow_wa_ctx`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.