drivers/gpu/drm/i915/gvt/scheduler.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/i915/gvt/scheduler.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/i915/gvt/scheduler.h
Extension
.h
Size
5066 bytes
Lines
170
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct intel_gvt_workload_scheduler {
	struct intel_vgpu *current_vgpu;
	struct intel_vgpu *next_vgpu;
	struct intel_vgpu_workload *current_workload[I915_NUM_ENGINES];
	bool need_reschedule;

	spinlock_t mmio_context_lock;
	/* can be null when owner is host */
	struct intel_vgpu *engine_owner[I915_NUM_ENGINES];

	wait_queue_head_t workload_complete_wq;
	struct task_struct *thread[I915_NUM_ENGINES];
	wait_queue_head_t waitq[I915_NUM_ENGINES];

	void *sched_data;
	const struct intel_gvt_sched_policy_ops *sched_ops;
};

#define INDIRECT_CTX_ADDR_MASK 0xffffffc0
#define INDIRECT_CTX_SIZE_MASK 0x3f
struct shadow_indirect_ctx {
	struct drm_i915_gem_object *obj;
	unsigned long guest_gma;
	unsigned long shadow_gma;
	void *shadow_va;
	u32 size;
};

#define PER_CTX_ADDR_MASK 0xfffff000
struct shadow_per_ctx {
	unsigned long guest_gma;
	unsigned long shadow_gma;
	unsigned valid;
};

struct intel_shadow_wa_ctx {
	struct shadow_indirect_ctx indirect_ctx;
	struct shadow_per_ctx per_ctx;

};

struct intel_vgpu_workload {
	struct intel_vgpu *vgpu;
	const struct intel_engine_cs *engine;
	struct i915_request *req;
	/* if this workload has been dispatched to i915? */
	bool dispatched;
	bool shadow;      /* if workload has done shadow of guest request */
	int status;

	struct intel_vgpu_mm *shadow_mm;
	struct list_head lri_shadow_mm; /* For PPGTT load cmd */

	/* different submission model may need different handler */
	int (*prepare)(struct intel_vgpu_workload *);
	int (*complete)(struct intel_vgpu_workload *);
	struct list_head list;

	DECLARE_BITMAP(pending_events, INTEL_GVT_EVENT_MAX);
	void *shadow_ring_buffer_va;

	/* execlist context information */
	struct execlist_ctx_descriptor_format ctx_desc;
	unsigned long rb_head, rb_tail, rb_ctl, rb_start, rb_len;
	unsigned long guest_rb_head;
	struct intel_vgpu_elsp_dwords elsp_dwords;
	bool emulate_schedule_in;
	atomic_t shadow_ctx_active;
	wait_queue_head_t shadow_ctx_status_wq;
	u64 ring_context_gpa;

	/* shadow batch buffer */
	struct list_head shadow_bb;
	struct intel_shadow_wa_ctx wa_ctx;

	/* oa registers */
	u32 oactxctrl;
	u32 flex_mmio[7];
};

struct intel_vgpu_shadow_bb {
	struct list_head list;
	struct drm_i915_gem_object *obj;
	struct i915_vma *vma;
	void *va;
	u32 *bb_start_cmd_va;
	unsigned long bb_offset;
	bool ppgtt;
};

Annotation

Implementation Notes