drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_cmn.h

File Facts

System

Linux kernel

Corpus path

drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_cmn.h

Extension

.h

Size

1184 bytes

Lines

43

Domain

Driver Families

Bucket

drivers/gpu

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• linux/types.h

Detected Declarations

• struct pxp_cmd_header
• enum pxp_status

Annotated Snippet

struct pxp_cmd_header {
	u32 api_version;
	u32 command_id;
	union {
		u32 status; /* out */
		u32 stream_id; /* in */
#define PXP_CMDHDR_EXTDATA_SESSION_VALID GENMASK(0, 0)
#define PXP_CMDHDR_EXTDATA_APP_TYPE GENMASK(1, 1)
#define PXP_CMDHDR_EXTDATA_SESSION_ID GENMASK(17, 2)
	};
	/* Length of the message (excluding the header) */
	u32 buffer_len;
} __packed;

#endif /* __INTEL_PXP_FW_INTERFACE_CMN_H__ */

Annotation

• Immediate include surface: `linux/types.h`.
• Detected declarations: `struct pxp_cmd_header`, `enum pxp_status`.
• Atlas domain: Driver Families / drivers/gpu.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.