drivers/gpu/drm/imagination/pvr_rogue_cr_defs_client.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/imagination/pvr_rogue_cr_defs_client.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/imagination/pvr_rogue_cr_defs_client.h
Extension
.h
Size
5924 bytes
Lines
160
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef PVR_ROGUE_CR_DEFS_CLIENT_H
#define PVR_ROGUE_CR_DEFS_CLIENT_H

/* clang-format off */

/*
 * This register controls the anti-aliasing mode of the Tiling Co-Processor, independent control is
 * provided in both X & Y axis.
 * This register needs to be set based on the ISP Samples Per Pixel a core supports.
 *
 * When ISP Samples Per Pixel = 1:
 * 2xmsaa is achieved by enabling Y - TE does AA on Y plane only
 * 4xmsaa is achieved by enabling Y and X - TE does AA on X and Y plane
 * 8xmsaa not supported by XE cores
 *
 * When ISP Samples Per Pixel = 2:
 * 2xmsaa is achieved by enabling X2 - does not affect TE
 * 4xmsaa is achieved by enabling Y and X2 - TE does AA on Y plane only
 * 8xmsaa is achieved by enabling Y, X and X2 - TE does AA on X and Y plane
 * 8xmsaa not supported by XE cores
 *
 * When ISP Samples Per Pixel = 4:
 * 2xmsaa is achieved by enabling X2 - does not affect TE
 * 4xmsaa is achieved by enabling Y2 and X2 - TE does AA on Y plane only
 * 8xmsaa not supported by XE cores
 */
/* Register ROGUE_CR_TE_AA */
#define ROGUE_CR_TE_AA 0x0C00U
#define ROGUE_CR_TE_AA_MASKFULL 0x000000000000000Full
/* Y2
 * Indicates 4xmsaa when X2 and Y2 are set to 1. This does not affect TE and is only used within
 * TPW.
 */
#define ROGUE_CR_TE_AA_Y2_SHIFT 3
#define ROGUE_CR_TE_AA_Y2_CLRMSK 0xFFFFFFF7
#define ROGUE_CR_TE_AA_Y2_EN 0x00000008
/* Y
 * Anti-Aliasing in Y Plane Enabled
 */
#define ROGUE_CR_TE_AA_Y_SHIFT 2
#define ROGUE_CR_TE_AA_Y_CLRMSK 0xFFFFFFFB
#define ROGUE_CR_TE_AA_Y_EN 0x00000004
/* X
 * Anti-Aliasing in X Plane Enabled
 */
#define ROGUE_CR_TE_AA_X_SHIFT 1
#define ROGUE_CR_TE_AA_X_CLRMSK 0xFFFFFFFD
#define ROGUE_CR_TE_AA_X_EN 0x00000002
/* X2
 * 2x Anti-Aliasing Enabled, affects PPP only
 */
#define ROGUE_CR_TE_AA_X2_SHIFT                             (0U)
#define ROGUE_CR_TE_AA_X2_CLRMSK                            (0xFFFFFFFEU)
#define ROGUE_CR_TE_AA_X2_EN                                (0x00000001U)

/* MacroTile Boundaries X Plane */
/* Register ROGUE_CR_TE_MTILE1 */
#define ROGUE_CR_TE_MTILE1 0x0C08
#define ROGUE_CR_TE_MTILE1_MASKFULL 0x0000000007FFFFFFull
/* X1 default: 0x00000004
 * X1 MacroTile boundary, left tile X for second column of macrotiles (16MT mode) - 32 pixels across
 * tile
 */
#define ROGUE_CR_TE_MTILE1_X1_SHIFT 18
#define ROGUE_CR_TE_MTILE1_X1_CLRMSK 0xF803FFFF
/* X2 default: 0x00000008
 * X2 MacroTile boundary, left tile X for third(16MT) column of macrotiles - 32 pixels across tile
 */
#define ROGUE_CR_TE_MTILE1_X2_SHIFT 9U
#define ROGUE_CR_TE_MTILE1_X2_CLRMSK 0xFFFC01FF
/* X3 default: 0x0000000c
 * X3 MacroTile boundary, left tile X for fourth column of macrotiles (16MT) - 32 pixels across tile
 */
#define ROGUE_CR_TE_MTILE1_X3_SHIFT 0
#define ROGUE_CR_TE_MTILE1_X3_CLRMSK 0xFFFFFE00

/* MacroTile Boundaries Y Plane. */
/* Register ROGUE_CR_TE_MTILE2 */
#define ROGUE_CR_TE_MTILE2 0x0C10
#define ROGUE_CR_TE_MTILE2_MASKFULL 0x0000000007FFFFFFull
/* Y1 default: 0x00000004
 * X1 MacroTile boundary, ltop tile Y for second column of macrotiles (16MT mode) - 32 pixels tile
 * height
 */
#define ROGUE_CR_TE_MTILE2_Y1_SHIFT 18
#define ROGUE_CR_TE_MTILE2_Y1_CLRMSK 0xF803FFFF
/* Y2 default: 0x00000008
 * X2 MacroTile boundary, top tile Y for third(16MT) column of macrotiles - 32 pixels tile height
 */
#define ROGUE_CR_TE_MTILE2_Y2_SHIFT 9

Annotation

Implementation Notes