drivers/gpu/drm/imagination/pvr_rogue_cr_defs.h

File Facts

System

Linux kernel

Corpus path

drivers/gpu/drm/imagination/pvr_rogue_cr_defs.h

Extension

.h

Size

342815 bytes

Lines

6309

Domain

Driver Families

Bucket

drivers/gpu

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef PVR_ROGUE_CR_DEFS_H
#define PVR_ROGUE_CR_DEFS_H

/* clang-format off */

#define ROGUE_CR_DEFS_REVISION 1

/* Register ROGUE_CR_RASTERISATION_INDIRECT */
#define ROGUE_CR_RASTERISATION_INDIRECT 0x8238U
#define ROGUE_CR_RASTERISATION_INDIRECT_MASKFULL 0x000000000000000FULL
#define ROGUE_CR_RASTERISATION_INDIRECT_ADDRESS_SHIFT 0U
#define ROGUE_CR_RASTERISATION_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFF0U

/* Register ROGUE_CR_PBE_INDIRECT */
#define ROGUE_CR_PBE_INDIRECT 0x83E0U
#define ROGUE_CR_PBE_INDIRECT_MASKFULL 0x000000000000000FULL
#define ROGUE_CR_PBE_INDIRECT_ADDRESS_SHIFT 0U
#define ROGUE_CR_PBE_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFF0U

/* Register ROGUE_CR_PBE_PERF_INDIRECT */
#define ROGUE_CR_PBE_PERF_INDIRECT 0x83D8U
#define ROGUE_CR_PBE_PERF_INDIRECT_MASKFULL 0x000000000000000FULL
#define ROGUE_CR_PBE_PERF_INDIRECT_ADDRESS_SHIFT 0U
#define ROGUE_CR_PBE_PERF_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFF0U

/* Register ROGUE_CR_TPU_PERF_INDIRECT */
#define ROGUE_CR_TPU_PERF_INDIRECT 0x83F0U
#define ROGUE_CR_TPU_PERF_INDIRECT_MASKFULL 0x0000000000000007ULL
#define ROGUE_CR_TPU_PERF_INDIRECT_ADDRESS_SHIFT 0U
#define ROGUE_CR_TPU_PERF_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFF8U

/* Register ROGUE_CR_RASTERISATION_PERF_INDIRECT */
#define ROGUE_CR_RASTERISATION_PERF_INDIRECT 0x8318U
#define ROGUE_CR_RASTERISATION_PERF_INDIRECT_MASKFULL 0x000000000000000FULL
#define ROGUE_CR_RASTERISATION_PERF_INDIRECT_ADDRESS_SHIFT 0U
#define ROGUE_CR_RASTERISATION_PERF_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFF0U

/* Register ROGUE_CR_TPU_MCU_L0_PERF_INDIRECT */
#define ROGUE_CR_TPU_MCU_L0_PERF_INDIRECT 0x8028U
#define ROGUE_CR_TPU_MCU_L0_PERF_INDIRECT_MASKFULL 0x0000000000000007ULL
#define ROGUE_CR_TPU_MCU_L0_PERF_INDIRECT_ADDRESS_SHIFT 0U
#define ROGUE_CR_TPU_MCU_L0_PERF_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFF8U

/* Register ROGUE_CR_USC_PERF_INDIRECT */
#define ROGUE_CR_USC_PERF_INDIRECT 0x8030U
#define ROGUE_CR_USC_PERF_INDIRECT_MASKFULL 0x000000000000000FULL
#define ROGUE_CR_USC_PERF_INDIRECT_ADDRESS_SHIFT 0U
#define ROGUE_CR_USC_PERF_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFF0U

/* Register ROGUE_CR_BLACKPEARL_INDIRECT */
#define ROGUE_CR_BLACKPEARL_INDIRECT 0x8388U
#define ROGUE_CR_BLACKPEARL_INDIRECT_MASKFULL 0x0000000000000003ULL
#define ROGUE_CR_BLACKPEARL_INDIRECT_ADDRESS_SHIFT 0U
#define ROGUE_CR_BLACKPEARL_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFFCU

/* Register ROGUE_CR_BLACKPEARL_PERF_INDIRECT */
#define ROGUE_CR_BLACKPEARL_PERF_INDIRECT 0x83F8U
#define ROGUE_CR_BLACKPEARL_PERF_INDIRECT_MASKFULL 0x0000000000000003ULL
#define ROGUE_CR_BLACKPEARL_PERF_INDIRECT_ADDRESS_SHIFT 0U
#define ROGUE_CR_BLACKPEARL_PERF_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFFCU

/* Register ROGUE_CR_TEXAS3_PERF_INDIRECT */
#define ROGUE_CR_TEXAS3_PERF_INDIRECT 0x83D0U
#define ROGUE_CR_TEXAS3_PERF_INDIRECT_MASKFULL 0x0000000000000007ULL
#define ROGUE_CR_TEXAS3_PERF_INDIRECT_ADDRESS_SHIFT 0U
#define ROGUE_CR_TEXAS3_PERF_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFF8U

/* Register ROGUE_CR_TEXAS_PERF_INDIRECT */
#define ROGUE_CR_TEXAS_PERF_INDIRECT 0x8288U
#define ROGUE_CR_TEXAS_PERF_INDIRECT_MASKFULL 0x0000000000000003ULL
#define ROGUE_CR_TEXAS_PERF_INDIRECT_ADDRESS_SHIFT 0U
#define ROGUE_CR_TEXAS_PERF_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFFCU

/* Register ROGUE_CR_BX_TU_PERF_INDIRECT */
#define ROGUE_CR_BX_TU_PERF_INDIRECT 0xC900U
#define ROGUE_CR_BX_TU_PERF_INDIRECT_MASKFULL 0x0000000000000003ULL
#define ROGUE_CR_BX_TU_PERF_INDIRECT_ADDRESS_SHIFT 0U
#define ROGUE_CR_BX_TU_PERF_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFFCU

/* Register ROGUE_CR_CLK_CTRL */
#define ROGUE_CR_CLK_CTRL 0x0000U
#define ROGUE_CR_CLK_CTRL__PBE2_XE__MASKFULL 0xFFFFFF003F3FFFFFULL
#define ROGUE_CR_CLK_CTRL__S7_TOP__MASKFULL 0xCFCF03000F3F3F0FULL
#define ROGUE_CR_CLK_CTRL_MASKFULL 0xFFFFFF003F3FFFFFULL
#define ROGUE_CR_CLK_CTRL_BIF_TEXAS_SHIFT 62U
#define ROGUE_CR_CLK_CTRL_BIF_TEXAS_CLRMSK 0x3FFFFFFFFFFFFFFFULL
#define ROGUE_CR_CLK_CTRL_BIF_TEXAS_OFF 0x0000000000000000ULL
#define ROGUE_CR_CLK_CTRL_BIF_TEXAS_ON 0x4000000000000000ULL
#define ROGUE_CR_CLK_CTRL_BIF_TEXAS_AUTO 0x8000000000000000ULL
#define ROGUE_CR_CLK_CTRL_IPP_SHIFT 60U

Annotation

• Atlas domain: Driver Families / drivers/gpu.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.