drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h
Extension
.h
Size
8366 bytes
Lines
267
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct rogue_fwif_dma_addr {
	aligned_u64 dev_addr;
	u32 fw_addr;
	u32 padding;
} __aligned(8);

struct rogue_fwif_ufo {
	u32 addr;
	u32 value;
};

#define ROGUE_FWIF_UFO_ADDR_IS_SYNC_CHECKPOINT (1)

struct rogue_fwif_sync_checkpoint {
	u32 state;
	u32 fw_ref_count;
};

struct rogue_fwif_cleanup_ctl {
	/* Number of commands received by the FW */
	u32 submitted_commands;
	/* Number of commands executed by the FW */
	u32 executed_commands;
} __aligned(8);

/*
 * Used to share frame numbers across UM-KM-FW,
 * frame number is set in UM,
 * frame number is required in both KM for HTB and FW for FW trace.
 *
 * May be used to house Kick flags in the future.
 */
struct rogue_fwif_cmd_common {
	/* associated frame number */
	u32 frame_num;
};

/*
 * Geometry and fragment commands require set of firmware addresses that are stored in the Kernel.
 * Client has handle(s) to Kernel containers storing these addresses, instead of raw addresses. We
 * have to patch/write these addresses in KM to prevent UM from controlling FW addresses directly.
 * Typedefs for geometry and fragment commands are shared between Client and Firmware (both
 * single-BVNC). Kernel is implemented in a multi-BVNC manner, so it can't use geometry|fragment
 * CMD type definitions directly. Therefore we have a SHARED block that is shared between UM-KM-FW
 * across all BVNC configurations.
 */
struct rogue_fwif_cmd_geom_frag_shared {
	/* Common command attributes */
	struct rogue_fwif_cmd_common cmn;

	/*
	 * RTData associated with this command, this is used for context
	 * selection and for storing out HW-context, when TA is switched out for
	 * continuing later
	 */
	u32 hwrt_data_fw_addr;

	/* Supported PR Buffers like Z/S/MSAA Scratch */
	u32 pr_buffer_fw_addr[ROGUE_FWIF_PRBUFFER_MAXSUPPORTED];
};

/*
 * Client Circular Command Buffer (CCCB) control structure.
 * This is shared between the Server and the Firmware and holds byte offsets
 * into the CCCB as well as the wrapping mask to aid wrap around. A given
 * snapshot of this queue with Cmd 1 running on the GPU might be:
 *
 *          Roff                           Doff                 Woff
 * [..........|-1----------|=2===|=3===|=4===|~5~~~~|~6~~~~|~7~~~~|..........]
 *            <      runnable commands       ><   !ready to run   >
 *
 * Cmd 1    : Currently executing on the GPU data master.
 * Cmd 2,3,4: Fence dependencies met, commands runnable.
 * Cmd 5... : Fence dependency not met yet.
 */
struct rogue_fwif_cccb_ctl {
	/* Host write offset into CCB. This must be aligned to 16 bytes. */
	u32 write_offset;
	/*
	 * Firmware read offset into CCB. Points to the command that is runnable
	 * on GPU, if R!=W
	 */
	u32 read_offset;
	/*
	 * Firmware fence dependency offset. Points to commands not ready, i.e.
	 * fence dependencies are not met.
	 */
	u32 dep_offset;
	/* Offset wrapping mask, total capacity in bytes of the CCB-1 */
	u32 wrap_mask;

Annotation

Implementation Notes