drivers/gpu/drm/imagination/pvr_rogue_meta.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/imagination/pvr_rogue_meta.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/imagination/pvr_rogue_meta.h
Extension
.h
Size
13623 bytes
Lines
357
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct rogue_meta_ldr_block_hdr {
	u32 dev_id;
	u32 sl_code;
	u32 sl_data;
	u16 pc_ctrl;
	u16 crc;
};

/* High level data stream block structure. */
struct rogue_meta_ldr_l1_data_blk {
	u16 cmd;
	u16 length;
	u32 next;
	u32 cmd_data[4];
};

/* High level data stream block structure. */
struct rogue_meta_ldr_l2_data_blk {
	u16 tag;
	u16 length;
	u32 block_data[4];
};

/* Config command structure. */
struct rogue_meta_ldr_cfg_blk {
	u32 type;
	u32 block_data[4];
};

/* Block type definitions */
#define ROGUE_META_LDR_COMMENT_TYPE_MASK (0x0010U)
#define ROGUE_META_LDR_BLK_IS_COMMENT(x) (((x) & ROGUE_META_LDR_COMMENT_TYPE_MASK) != 0U)

/*
 * Command definitions
 *  Value   Name            Description
 *  0       LoadMem         Load memory with binary data.
 *  1       LoadCore        Load a set of core registers.
 *  2       LoadMMReg       Load a set of memory mapped registers.
 *  3       StartThreads    Set each thread PC and SP, then enable threads.
 *  4       ZeroMem         Zeros a memory region.
 *  5       Config          Perform a configuration command.
 */
#define ROGUE_META_LDR_CMD_MASK (0x000FU)

#define ROGUE_META_LDR_CMD_LOADMEM (0x0000U)
#define ROGUE_META_LDR_CMD_LOADCORE (0x0001U)
#define ROGUE_META_LDR_CMD_LOADMMREG (0x0002U)
#define ROGUE_META_LDR_CMD_START_THREADS (0x0003U)
#define ROGUE_META_LDR_CMD_ZEROMEM (0x0004U)
#define ROGUE_META_LDR_CMD_CONFIG (0x0005U)

/*
 * Config Command definitions
 *  Value   Name        Description
 *  0       Pause       Pause for x times 100 instructions
 *  1       Read        Read a value from register - No value return needed.
 *                      Utilises effects of issuing reads to certain registers
 *  2       Write       Write to mem location
 *  3       MemSet      Set mem to value
 *  4       MemCheck    check mem for specific value.
 */
#define ROGUE_META_LDR_CFG_PAUSE (0x0000)
#define ROGUE_META_LDR_CFG_READ (0x0001)
#define ROGUE_META_LDR_CFG_WRITE (0x0002)
#define ROGUE_META_LDR_CFG_MEMSET (0x0003)
#define ROGUE_META_LDR_CFG_MEMCHECK (0x0004)

/*
 ******************************************************************************
 * ROGUE FW segmented MMU definitions
 ******************************************************************************
 */
/* All threads can access the segment. */
#define ROGUE_FW_SEGMMU_ALLTHRS (0xf << 8U)
/* Writable. */
#define ROGUE_FW_SEGMMU_WRITEABLE (0x1U << 1U)
/* All threads can access and writable. */
#define ROGUE_FW_SEGMMU_ALLTHRS_WRITEABLE \
	(ROGUE_FW_SEGMMU_ALLTHRS | ROGUE_FW_SEGMMU_WRITEABLE)

/* Direct map region 10 used for mapping GPU memory - max 8MB. */
#define ROGUE_FW_SEGMMU_DMAP_GPU_ID (10U)
#define ROGUE_FW_SEGMMU_DMAP_GPU_ADDR_START (0x07000000U)
#define ROGUE_FW_SEGMMU_DMAP_GPU_MAX_SIZE (0x00800000U)

/* Segment IDs. */
#define ROGUE_FW_SEGMMU_DATA_ID (1U)
#define ROGUE_FW_SEGMMU_BOOTLDR_ID (2U)
#define ROGUE_FW_SEGMMU_TEXT_ID (ROGUE_FW_SEGMMU_BOOTLDR_ID)

Annotation

Implementation Notes