drivers/gpu/drm/imagination/pvr_rogue_mips.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/imagination/pvr_rogue_mips.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/imagination/pvr_rogue_mips.h
Extension
.h
Size
14351 bytes
Lines
336
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct rogue_mipsfw_boot_data {
	u64 stack_phys_addr;
	u64 reg_base;
	u64 pt_phys_addr[ROGUE_MIPSFW_MAX_NUM_PAGETABLE_PAGES];
	u32 pt_log2_page_size;
	u32 pt_num_pages;
	u32 reserved1;
	u32 reserved2;
};

#define ROGUE_MIPSFW_GET_OFFSET_IN_DWORDS(offset) ((offset) / sizeof(u32))
#define ROGUE_MIPSFW_GET_OFFSET_IN_QWORDS(offset) ((offset) / sizeof(u64))

/* Used for compatibility checks. */
#define ROGUE_MIPSFW_ARCHTYPE_VER_CLRMSK (0xFFFFE3FFU)
#define ROGUE_MIPSFW_ARCHTYPE_VER_SHIFT (10U)
#define ROGUE_MIPSFW_CORE_ID_VALUE (0x001U)
#define ROGUE_FW_PROCESSOR_MIPS "MIPS"

/* microAptivAP cache line size. */
#define ROGUE_MIPSFW_MICROAPTIVEAP_CACHELINE_SIZE (16U)

/*
 * The SOCIF transactions are identified with the top 16 bits of the physical address emitted by
 * the MIPS.
 */
#define ROGUE_MIPSFW_WRAPPER_CONFIG_REGBANK_ADDR_ALIGN (16U)

/* Values to put in the MIPS selectors for performance counters. */
/* Icache accesses in COUNTER0. */
#define ROGUE_MIPSFW_PERF_COUNT_CTRL_ICACHE_ACCESSES_C0 (9U)
/* Icache misses in COUNTER1. */
#define ROGUE_MIPSFW_PERF_COUNT_CTRL_ICACHE_MISSES_C1 (9U)

/* Dcache accesses in COUNTER0. */
#define ROGUE_MIPSFW_PERF_COUNT_CTRL_DCACHE_ACCESSES_C0 (10U)
/* Dcache misses in COUNTER1. */
#define ROGUE_MIPSFW_PERF_COUNT_CTRL_DCACHE_MISSES_C1 (11U)

/* ITLB instruction accesses in COUNTER0. */
#define ROGUE_MIPSFW_PERF_COUNT_CTRL_ITLB_INSTR_ACCESSES_C0 (5U)
/* JTLB instruction accesses misses in COUNTER1. */
#define ROGUE_MIPSFW_PERF_COUNT_CTRL_JTLB_INSTR_MISSES_C1 (7U)

  /* Instructions completed in COUNTER0. */
#define ROGUE_MIPSFW_PERF_COUNT_CTRL_INSTR_COMPLETED_C0 (1U)
/* JTLB data misses in COUNTER1. */
#define ROGUE_MIPSFW_PERF_COUNT_CTRL_JTLB_DATA_MISSES_C1 (8U)

/* Shift for the Event field in the MIPS perf ctrl registers. */
#define ROGUE_MIPSFW_PERF_COUNT_CTRL_EVENT_SHIFT (5U)

/* Additional flags for performance counters. See MIPS manual for further reference. */
#define ROGUE_MIPSFW_PERF_COUNT_CTRL_COUNT_USER_MODE (8U)
#define ROGUE_MIPSFW_PERF_COUNT_CTRL_COUNT_KERNEL_MODE (2U)
#define ROGUE_MIPSFW_PERF_COUNT_CTRL_COUNT_EXL (1U)

#define ROGUE_MIPSFW_C0_NBHWIRQ	8

/* Macros to decode C0_Cause register. */
#define ROGUE_MIPSFW_C0_CAUSE_EXCCODE(cause) (((cause) & 0x7c) >> 2)
#define ROGUE_MIPSFW_C0_CAUSE_EXCCODE_FWERROR 9
/* Use only when Coprocessor Unusable exception. */
#define ROGUE_MIPSFW_C0_CAUSE_UNUSABLE_UNIT(cause) (((cause) >> 28) & 0x3)
#define ROGUE_MIPSFW_C0_CAUSE_PENDING_HWIRQ(cause) (((cause) & 0x3fc00) >> 10)
#define ROGUE_MIPSFW_C0_CAUSE_FDCIPENDING BIT(21)
#define ROGUE_MIPSFW_C0_CAUSE_IV BIT(23)
#define ROGUE_MIPSFW_C0_CAUSE_IC BIT(25)
#define ROGUE_MIPSFW_C0_CAUSE_PCIPENDING BIT(26)
#define ROGUE_MIPSFW_C0_CAUSE_TIPENDING BIT(30)
#define ROGUE_MIPSFW_C0_CAUSE_BRANCH_DELAY BIT(31)

/* Macros to decode C0_Debug register. */
#define ROGUE_MIPSFW_C0_DEBUG_EXCCODE(debug) (((debug) >> 10) & 0x1f)
#define ROGUE_MIPSFW_C0_DEBUG_DSS BIT(0)
#define ROGUE_MIPSFW_C0_DEBUG_DBP BIT(1)
#define ROGUE_MIPSFW_C0_DEBUG_DDBL BIT(2)
#define ROGUE_MIPSFW_C0_DEBUG_DDBS BIT(3)
#define ROGUE_MIPSFW_C0_DEBUG_DIB BIT(4)
#define ROGUE_MIPSFW_C0_DEBUG_DINT BIT(5)
#define ROGUE_MIPSFW_C0_DEBUG_DIBIMPR BIT(6)
#define ROGUE_MIPSFW_C0_DEBUG_DDBLIMPR BIT(18)
#define ROGUE_MIPSFW_C0_DEBUG_DDBSIMPR BIT(19)
#define ROGUE_MIPSFW_C0_DEBUG_IEXI BIT(20)
#define ROGUE_MIPSFW_C0_DEBUG_DBUSEP BIT(21)
#define ROGUE_MIPSFW_C0_DEBUG_CACHEEP BIT(22)
#define ROGUE_MIPSFW_C0_DEBUG_MCHECKP BIT(23)
#define ROGUE_MIPSFW_C0_DEBUG_IBUSEP BIT(24)
#define ROGUE_MIPSFW_C0_DEBUG_DM BIT(30)
#define ROGUE_MIPSFW_C0_DEBUG_DBD BIT(31)

Annotation

Implementation Notes