drivers/gpu/drm/imagination/pvr_vm_mips.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/imagination/pvr_vm_mips.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/imagination/pvr_vm_mips.c- Extension
.c- Size
- 6615 bytes
- Lines
- 238
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
pvr_device.hpvr_fw_mips.hpvr_gem.hpvr_mmu.hpvr_rogue_mips.hpvr_vm.hpvr_vm_mips.hdrm/drm_managed.hlinux/dma-mapping.hlinux/err.hlinux/slab.hlinux/types.hlinux/vmalloc.h
Detected Declarations
function pvr_vm_mips_initfunction pvr_vm_mips_finifunction get_mips_pte_flagsfunction pvr_vm_mips_mapfunction pvr_vm_mips_unmap
Annotated Snippet
if (!mips_data->pt_pages[page_nr]) {
err = -ENOMEM;
goto err_free_pages;
}
mips_data->pt_dma_addr[page_nr] = dma_map_page(dev, mips_data->pt_pages[page_nr], 0,
PAGE_SIZE, DMA_TO_DEVICE);
if (dma_mapping_error(dev, mips_data->pt_dma_addr[page_nr])) {
err = -ENOMEM;
__free_page(mips_data->pt_pages[page_nr]);
goto err_free_pages;
}
}
mips_data->pt = vmap(mips_data->pt_pages, pt_size >> PAGE_SHIFT, VM_MAP,
pgprot_writecombine(PAGE_KERNEL));
if (!mips_data->pt) {
err = -ENOMEM;
goto err_free_pages;
}
mips_data->pfn_mask = (phys_bus_width > 32) ? ROGUE_MIPSFW_ENTRYLO_PFN_MASK_ABOVE_32BIT :
ROGUE_MIPSFW_ENTRYLO_PFN_MASK;
mips_data->cache_policy = (phys_bus_width > 32) ? ROGUE_MIPSFW_CACHED_POLICY_ABOVE_32BIT :
ROGUE_MIPSFW_CACHED_POLICY;
pvr_dev->fw_dev.processor_data.mips_data = mips_data;
return 0;
err_free_pages:
while (--page_nr >= 0) {
dma_unmap_page(from_pvr_device(pvr_dev)->dev,
mips_data->pt_dma_addr[page_nr], PAGE_SIZE, DMA_TO_DEVICE);
__free_page(mips_data->pt_pages[page_nr]);
}
return err;
}
/**
* pvr_vm_mips_fini() - Release MIPS FW pagetable
* @pvr_dev: Target PowerVR device.
*/
void
pvr_vm_mips_fini(struct pvr_device *pvr_dev)
{
struct pvr_fw_device *fw_dev = &pvr_dev->fw_dev;
struct pvr_fw_mips_data *mips_data = fw_dev->processor_data.mips_data;
vunmap(mips_data->pt);
for (int page_nr = PVR_MIPS_PT_PAGE_COUNT - 1; page_nr >= 0; page_nr--) {
dma_unmap_page(from_pvr_device(pvr_dev)->dev,
mips_data->pt_dma_addr[page_nr], PAGE_SIZE, DMA_TO_DEVICE);
__free_page(mips_data->pt_pages[page_nr]);
}
fw_dev->processor_data.mips_data = NULL;
}
static u32
get_mips_pte_flags(bool read, bool write, u32 cache_policy)
{
u32 flags = 0;
if (read && write) /* Read/write. */
flags |= ROGUE_MIPSFW_ENTRYLO_DIRTY_EN;
else if (write) /* Write only. */
flags |= ROGUE_MIPSFW_ENTRYLO_READ_INHIBIT_EN;
else
WARN_ON(!read);
flags |= cache_policy << ROGUE_MIPSFW_ENTRYLO_CACHE_POLICY_SHIFT;
flags |= ROGUE_MIPSFW_ENTRYLO_VALID_EN | ROGUE_MIPSFW_ENTRYLO_GLOBAL_EN;
return flags;
}
/**
* pvr_vm_mips_map() - Map a FW object into MIPS address space
* @pvr_dev: Target PowerVR device.
* @fw_obj: FW object to map.
*
* Returns:
* * 0 on success,
* * -%EINVAL if object does not reside within FW address space, or
Annotation
- Immediate include surface: `pvr_device.h`, `pvr_fw_mips.h`, `pvr_gem.h`, `pvr_mmu.h`, `pvr_rogue_mips.h`, `pvr_vm.h`, `pvr_vm_mips.h`, `drm/drm_managed.h`.
- Detected declarations: `function pvr_vm_mips_init`, `function pvr_vm_mips_fini`, `function get_mips_pte_flags`, `function pvr_vm_mips_map`, `function pvr_vm_mips_unmap`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.