drivers/gpu/drm/kmb/kmb_regs.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/kmb/kmb_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/kmb/kmb_regs.h
Extension
.h
Size
30323 bytes
Lines
729
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __KMB_REGS_H__
#define __KMB_REGS_H__

/***************************************************************************
 *		   LCD controller control register defines
 ***************************************************************************/
#define LCD_CONTROL				(0x4 * 0x000)
#define LCD_CTRL_PROGRESSIVE			  (0 << 0)
#define LCD_CTRL_INTERLACED			  BIT(0)
#define LCD_CTRL_ENABLE				  BIT(1)
#define LCD_CTRL_VL1_ENABLE			  BIT(2)
#define LCD_CTRL_VL2_ENABLE			  BIT(3)
#define LCD_CTRL_GL1_ENABLE			  BIT(4)
#define LCD_CTRL_GL2_ENABLE			  BIT(5)
#define LCD_CTRL_ALPHA_BLEND_VL1		  (0 << 6)
#define LCD_CTRL_ALPHA_BLEND_VL2		  BIT(6)
#define LCD_CTRL_ALPHA_BLEND_GL1		  (2 << 6)
#define LCD_CTRL_ALPHA_BLEND_GL2		  (3 << 6)
#define LCD_CTRL_ALPHA_TOP_VL1			  (0 << 8)
#define LCD_CTRL_ALPHA_TOP_VL2			  BIT(8)
#define LCD_CTRL_ALPHA_TOP_GL1			  (2 << 8)
#define LCD_CTRL_ALPHA_TOP_GL2			  (3 << 8)
#define LCD_CTRL_ALPHA_MIDDLE_VL1		  (0 << 10)
#define LCD_CTRL_ALPHA_MIDDLE_VL2		  BIT(10)
#define LCD_CTRL_ALPHA_MIDDLE_GL1		  (2 << 10)
#define LCD_CTRL_ALPHA_MIDDLE_GL2		  (3 << 10)
#define LCD_CTRL_ALPHA_BOTTOM_VL1		  (0 << 12)
#define LCD_CTRL_ALPHA_BOTTOM_VL2		  BIT(12)
#define LCD_CTRL_ALPHA_BOTTOM_GL1		  (2 << 12)
#define LCD_CTRL_ALPHA_BOTTOM_GL2		  (3 << 12)
#define LCD_CTRL_TIM_GEN_ENABLE			  BIT(14)
#define LCD_CTRL_CONTINUOUS			  (0 << 15)
#define LCD_CTRL_ONE_SHOT			  BIT(15)
#define LCD_CTRL_PWM0_EN			  BIT(16)
#define LCD_CTRL_PWM1_EN			  BIT(17)
#define LCD_CTRL_PWM2_EN			  BIT(18)
#define LCD_CTRL_OUTPUT_DISABLED		  (0 << 19)
#define LCD_CTRL_OUTPUT_ENABLED			  BIT(19)
#define LCD_CTRL_BPORCH_ENABLE			  BIT(21)
#define LCD_CTRL_FPORCH_ENABLE			  BIT(22)
#define LCD_CTRL_ALPHA_BLEND_BKGND_DISABLE	  BIT(23)
#define LCD_CTRL_PIPELINE_DMA			  BIT(28)
#define LCD_CTRL_VHSYNC_IDLE_LVL		  BIT(31)
#define LCD_CTRL_ALPHA_ALL			  (0xff << 6)

/* interrupts */
#define LCD_INT_STATUS				(0x4 * 0x001)
#define LCD_INT_EOF				  BIT(0)
#define LCD_INT_LINE_CMP			  BIT(1)
#define LCD_INT_VERT_COMP			  BIT(2)
#define LAYER0_DMA_DONE				  BIT(3)
#define LAYER0_DMA_IDLE				  BIT(4)
#define LAYER0_DMA_FIFO_OVERFLOW		  BIT(5)
#define LAYER0_DMA_FIFO_UNDERFLOW		  BIT(6)
#define LAYER0_DMA_CB_FIFO_OVERFLOW		  BIT(7)
#define LAYER0_DMA_CB_FIFO_UNDERFLOW		  BIT(8)
#define LAYER0_DMA_CR_FIFO_OVERFLOW		  BIT(9)
#define LAYER0_DMA_CR_FIFO_UNDERFLOW		  BIT(10)
#define LAYER1_DMA_DONE				  BIT(11)
#define LAYER1_DMA_IDLE				  BIT(12)
#define LAYER1_DMA_FIFO_OVERFLOW		  BIT(13)
#define LAYER1_DMA_FIFO_UNDERFLOW		  BIT(14)
#define LAYER1_DMA_CB_FIFO_OVERFLOW		  BIT(15)
#define LAYER1_DMA_CB_FIFO_UNDERFLOW		  BIT(16)
#define LAYER1_DMA_CR_FIFO_OVERFLOW		  BIT(17)
#define LAYER1_DMA_CR_FIFO_UNDERFLOW		  BIT(18)
#define LAYER2_DMA_DONE				  BIT(19)
#define LAYER2_DMA_IDLE				  BIT(20)
#define LAYER2_DMA_FIFO_OVERFLOW		  BIT(21)
#define LAYER2_DMA_FIFO_UNDERFLOW		  BIT(22)
#define LAYER3_DMA_DONE				  BIT(23)
#define LAYER3_DMA_IDLE				  BIT(24)
#define LAYER3_DMA_FIFO_OVERFLOW		  BIT(25)
#define LAYER3_DMA_FIFO_UNDERFLOW		  BIT(26)
#define LCD_INT_LAYER				  (0x07fffff8)
#define LCD_INT_ENABLE				(0x4 * 0x002)
#define LCD_INT_CLEAR				(0x4 * 0x003)
#define LCD_LINE_COUNT				(0x4 * 0x004)
#define LCD_LINE_COMPARE			(0x4 * 0x005)
#define LCD_VSTATUS				(0x4 * 0x006)

/*LCD_VSTATUS_COMPARE Vertcal interval in which to generate vertcal
 * interval interrupt
 */
/* BITS 13 and 14 */
#define LCD_VSTATUS_COMPARE			(0x4 * 0x007)
#define LCD_VSTATUS_VERTICAL_STATUS_MASK	  (3 << 13)
#define LCD_VSTATUS_COMPARE_VSYNC		  (0 << 13)
#define LCD_VSTATUS_COMPARE_BACKPORCH		  BIT(13)
#define LCD_VSTATUS_COMPARE_ACTIVE		  (2 << 13)

Annotation

Implementation Notes