drivers/gpu/drm/lima/lima_regs.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/lima/lima_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/lima/lima_regs.h
Extension
.h
Size
12668 bytes
Lines
300
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __LIMA_REGS_H__
#define __LIMA_REGS_H__

/* This file's register definition is collected from the
 * official ARM Mali Utgard GPU kernel driver source code
 */

/* PMU regs */
#define LIMA_PMU_POWER_UP                  0x00
#define LIMA_PMU_POWER_DOWN                0x04
#define   LIMA_PMU_POWER_GP0_MASK          BIT(0)
#define   LIMA_PMU_POWER_L2_MASK           BIT(1)
#define   LIMA_PMU_POWER_PP_MASK(i)        BIT(2 + i)

/*
 * On Mali450 each block automatically starts up its corresponding L2
 * and the PPs are not fully independent controllable.
 * Instead PP0, PP1-3 and PP4-7 can be turned on or off.
 */
#define   LIMA450_PMU_POWER_PP0_MASK       BIT(1)
#define   LIMA450_PMU_POWER_PP13_MASK      BIT(2)
#define   LIMA450_PMU_POWER_PP47_MASK      BIT(3)

#define LIMA_PMU_STATUS                    0x08
#define LIMA_PMU_INT_MASK                  0x0C
#define LIMA_PMU_INT_RAWSTAT               0x10
#define LIMA_PMU_INT_CLEAR                 0x18
#define   LIMA_PMU_INT_CMD_MASK            BIT(0)
#define LIMA_PMU_SW_DELAY                  0x1C

/* L2 cache regs */
#define LIMA_L2_CACHE_SIZE                   0x0004
#define LIMA_L2_CACHE_STATUS                 0x0008
#define   LIMA_L2_CACHE_STATUS_COMMAND_BUSY  BIT(0)
#define   LIMA_L2_CACHE_STATUS_DATA_BUSY     BIT(1)
#define LIMA_L2_CACHE_COMMAND                0x0010
#define   LIMA_L2_CACHE_COMMAND_CLEAR_ALL    BIT(0)
#define LIMA_L2_CACHE_CLEAR_PAGE             0x0014
#define LIMA_L2_CACHE_MAX_READS              0x0018
#define LIMA_L2_CACHE_ENABLE                 0x001C
#define   LIMA_L2_CACHE_ENABLE_ACCESS        BIT(0)
#define   LIMA_L2_CACHE_ENABLE_READ_ALLOCATE BIT(1)
#define LIMA_L2_CACHE_PERFCNT_SRC0           0x0020
#define LIMA_L2_CACHE_PERFCNT_VAL0           0x0024
#define LIMA_L2_CACHE_PERFCNT_SRC1           0x0028
#define LIMA_L2_CACHE_ERFCNT_VAL1            0x002C

/* GP regs */
#define LIMA_GP_VSCL_START_ADDR                0x00
#define LIMA_GP_VSCL_END_ADDR                  0x04
#define LIMA_GP_PLBUCL_START_ADDR              0x08
#define LIMA_GP_PLBUCL_END_ADDR                0x0c
#define LIMA_GP_PLBU_ALLOC_START_ADDR          0x10
#define LIMA_GP_PLBU_ALLOC_END_ADDR            0x14
#define LIMA_GP_CMD                            0x20
#define   LIMA_GP_CMD_START_VS                 BIT(0)
#define   LIMA_GP_CMD_START_PLBU               BIT(1)
#define   LIMA_GP_CMD_UPDATE_PLBU_ALLOC        BIT(4)
#define   LIMA_GP_CMD_RESET                    BIT(5)
#define   LIMA_GP_CMD_FORCE_HANG               BIT(6)
#define   LIMA_GP_CMD_STOP_BUS                 BIT(9)
#define   LIMA_GP_CMD_SOFT_RESET               BIT(10)
#define LIMA_GP_INT_RAWSTAT                    0x24
#define LIMA_GP_INT_CLEAR                      0x28
#define LIMA_GP_INT_MASK                       0x2C
#define LIMA_GP_INT_STAT                       0x30
#define   LIMA_GP_IRQ_VS_END_CMD_LST           BIT(0)
#define   LIMA_GP_IRQ_PLBU_END_CMD_LST         BIT(1)
#define   LIMA_GP_IRQ_PLBU_OUT_OF_MEM          BIT(2)
#define   LIMA_GP_IRQ_VS_SEM_IRQ               BIT(3)
#define   LIMA_GP_IRQ_PLBU_SEM_IRQ             BIT(4)
#define   LIMA_GP_IRQ_HANG                     BIT(5)
#define   LIMA_GP_IRQ_FORCE_HANG               BIT(6)
#define   LIMA_GP_IRQ_PERF_CNT_0_LIMIT         BIT(7)
#define   LIMA_GP_IRQ_PERF_CNT_1_LIMIT         BIT(8)
#define   LIMA_GP_IRQ_WRITE_BOUND_ERR          BIT(9)
#define   LIMA_GP_IRQ_SYNC_ERROR               BIT(10)
#define   LIMA_GP_IRQ_AXI_BUS_ERROR            BIT(11)
#define   LIMA_GP_IRQ_AXI_BUS_STOPPED          BIT(12)
#define   LIMA_GP_IRQ_VS_INVALID_CMD           BIT(13)
#define   LIMA_GP_IRQ_PLB_INVALID_CMD          BIT(14)
#define   LIMA_GP_IRQ_RESET_COMPLETED          BIT(19)
#define   LIMA_GP_IRQ_SEMAPHORE_UNDERFLOW      BIT(20)
#define   LIMA_GP_IRQ_SEMAPHORE_OVERFLOW       BIT(21)
#define   LIMA_GP_IRQ_PTR_ARRAY_OUT_OF_BOUNDS  BIT(22)
#define LIMA_GP_WRITE_BOUND_LOW                0x34
#define LIMA_GP_PERF_CNT_0_ENABLE              0x3C
#define LIMA_GP_PERF_CNT_1_ENABLE              0x40
#define LIMA_GP_PERF_CNT_0_SRC                 0x44
#define LIMA_GP_PERF_CNT_1_SRC                 0x48

Annotation

Implementation Notes