drivers/gpu/drm/loongson/lsdc_pixpll.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/loongson/lsdc_pixpll.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/loongson/lsdc_pixpll.c- Extension
.c- Size
- 12637 bytes
- Lines
- 485
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/delay.hdrm/drm_managed.hdrm/drm_print.hlsdc_drv.h
Detected Declarations
struct lsdc_pixpll_regstruct clk_to_pixpll_parms_lookup_tfunction lsdc_pixel_pll_freefunction lsdc_pixel_pll_setupfunction lsdc_pixpll_findfunction motherboardfunction __pixpll_rregfunction __pixpll_wregfunction __pixpll_ops_powerupfunction __pixpll_ops_powerdownfunction __pixpll_ops_onfunction __pixpll_ops_offfunction __pixpll_ops_bypassfunction __pixpll_ops_unbypassfunction __pixpll_ops_untoggle_paramfunction __pixpll_ops_set_paramfunction __pixpll_ops_toggle_paramfunction __pixpll_ops_wait_lockedfunction lsdc_pixpll_updatefunction lsdc_pixpll_get_freqfunction lsdc_pixpll_printfunction lsdc_pixpll_init
Annotated Snippet
struct lsdc_pixpll_reg {
/* Byte 0 ~ Byte 3 */
unsigned div_out : 7; /* 6 : 0 Output clock divider */
unsigned _reserved_1_ : 14; /* 20 : 7 */
unsigned loopc : 9; /* 29 : 21 Clock multiplier */
unsigned _reserved_2_ : 2; /* 31 : 30 */
/* Byte 4 ~ Byte 7 */
unsigned div_ref : 7; /* 38 : 32 Input clock divider */
unsigned locked : 1; /* 39 PLL locked indicator */
unsigned sel_out : 1; /* 40 output clk selector */
unsigned _reserved_3_ : 2; /* 42 : 41 */
unsigned set_param : 1; /* 43 Trigger the update */
unsigned bypass : 1; /* 44 */
unsigned powerdown : 1; /* 45 */
unsigned _reserved_4_ : 18; /* 46 : 63 no use */
};
union lsdc_pixpll_reg_bitmap {
struct lsdc_pixpll_reg bitmap;
u32 w[2];
u64 d;
};
struct clk_to_pixpll_parms_lookup_t {
unsigned int clock; /* kHz */
unsigned short width;
unsigned short height;
unsigned short vrefresh;
/* Stores parameters for programming the Hardware PLLs */
unsigned short div_out;
unsigned short loopc;
unsigned short div_ref;
};
static const struct clk_to_pixpll_parms_lookup_t pixpll_parms_table[] = {
{148500, 1920, 1080, 60, 11, 49, 3}, /* 1920x1080@60Hz */
{141750, 1920, 1080, 60, 11, 78, 5}, /* 1920x1080@60Hz */
/* 1920x1080@50Hz */
{174500, 1920, 1080, 75, 17, 89, 3}, /* 1920x1080@75Hz */
{181250, 2560, 1080, 75, 8, 58, 4}, /* 2560x1080@75Hz */
{297000, 2560, 1080, 30, 8, 95, 4}, /* 3840x2160@30Hz */
{301992, 1920, 1080, 100, 10, 151, 5}, /* 1920x1080@100Hz */
{146250, 1680, 1050, 60, 16, 117, 5}, /* 1680x1050@60Hz */
{135000, 1280, 1024, 75, 10, 54, 4}, /* 1280x1024@75Hz */
{119000, 1680, 1050, 60, 20, 119, 5}, /* 1680x1050@60Hz */
{108000, 1600, 900, 60, 15, 81, 5}, /* 1600x900@60Hz */
/* 1280x1024@60Hz */
/* 1280x960@60Hz */
/* 1152x864@75Hz */
{106500, 1440, 900, 60, 19, 81, 4}, /* 1440x900@60Hz */
{88750, 1440, 900, 60, 16, 71, 5}, /* 1440x900@60Hz */
{83500, 1280, 800, 60, 17, 71, 5}, /* 1280x800@60Hz */
{71000, 1280, 800, 60, 20, 71, 5}, /* 1280x800@60Hz */
{74250, 1280, 720, 60, 22, 49, 3}, /* 1280x720@60Hz */
/* 1280x720@50Hz */
{78750, 1024, 768, 75, 16, 63, 5}, /* 1024x768@75Hz */
{75000, 1024, 768, 70, 29, 87, 4}, /* 1024x768@70Hz */
{65000, 1024, 768, 60, 20, 39, 3}, /* 1024x768@60Hz */
{51200, 1024, 600, 60, 25, 64, 5}, /* 1024x600@60Hz */
{57284, 832, 624, 75, 24, 55, 4}, /* 832x624@75Hz */
{49500, 800, 600, 75, 40, 99, 5}, /* 800x600@75Hz */
{50000, 800, 600, 72, 44, 88, 4}, /* 800x600@72Hz */
{40000, 800, 600, 60, 30, 36, 3}, /* 800x600@60Hz */
{36000, 800, 600, 56, 50, 72, 4}, /* 800x600@56Hz */
{31500, 640, 480, 75, 40, 63, 5}, /* 640x480@75Hz */
/* 640x480@73Hz */
{30240, 640, 480, 67, 62, 75, 4}, /* 640x480@67Hz */
{27000, 720, 576, 50, 50, 54, 4}, /* 720x576@60Hz */
{25175, 640, 480, 60, 85, 107, 5}, /* 640x480@60Hz */
{25200, 640, 480, 60, 50, 63, 5}, /* 640x480@60Hz */
/* 720x480@60Hz */
};
static void lsdc_pixel_pll_free(struct drm_device *ddev, void *data)
{
struct lsdc_pixpll *this = (struct lsdc_pixpll *)data;
iounmap(this->mmio);
kfree(this->priv);
Annotation
- Immediate include surface: `linux/delay.h`, `drm/drm_managed.h`, `drm/drm_print.h`, `lsdc_drv.h`.
- Detected declarations: `struct lsdc_pixpll_reg`, `struct clk_to_pixpll_parms_lookup_t`, `function lsdc_pixel_pll_free`, `function lsdc_pixel_pll_setup`, `function lsdc_pixpll_find`, `function motherboard`, `function __pixpll_rreg`, `function __pixpll_wreg`, `function __pixpll_ops_powerup`, `function __pixpll_ops_powerdown`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.