drivers/gpu/drm/loongson/lsdc_regs.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/loongson/lsdc_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/loongson/lsdc_regs.h
Extension
.h
Size
14920 bytes
Lines
407
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __LSDC_REGS_H__
#define __LSDC_REGS_H__

#include <linux/bitops.h>
#include <linux/types.h>

/*
 * PIXEL PLL Reference clock
 */
#define LSDC_PLL_REF_CLK_KHZ            100000

/*
 * Those PLL registers are relative to LSxxxxx_CFG_REG_BASE. xxxxx = 7A1000,
 * 7A2000, 2K2000, 2K1000 etc.
 */

/* LS7A1000 */

#define LS7A1000_PIXPLL0_REG            0x04B0
#define LS7A1000_PIXPLL1_REG            0x04C0

/* The DC, GPU, Graphic Memory Controller share the single gfxpll */
#define LS7A1000_PLL_GFX_REG            0x0490

#define LS7A1000_CONF_REG_BASE          0x10010000

/* LS7A2000 */

#define LS7A2000_PIXPLL0_REG            0x04B0
#define LS7A2000_PIXPLL1_REG            0x04C0

/* The DC, GPU, Graphic Memory Controller share the single gfxpll */
#define LS7A2000_PLL_GFX_REG            0x0490

#define LS7A2000_CONF_REG_BASE          0x10010000

/* For LSDC_CRTCx_CFG_REG */
#define CFG_PIX_FMT_MASK                GENMASK(2, 0)

enum lsdc_pixel_format {
	LSDC_PF_NONE = 0,
	LSDC_PF_XRGB444 = 1,    /* [12 bits] */
	LSDC_PF_XRGB555 = 2,    /* [15 bits] */
	LSDC_PF_XRGB565 = 3,    /* RGB [16 bits] */
	LSDC_PF_XRGB8888 = 4,   /* XRGB [32 bits] */
};

/*
 * Each crtc has two set fb address registers usable, FB_REG_IN_USING bit of
 * LSDC_CRTCx_CFG_REG indicate which fb address register is in using by the
 * CRTC currently. CFG_PAGE_FLIP is used to trigger the switch, the switching
 * will be finished at the very next vblank. Trigger it again if you want to
 * switch back.
 *
 * If FB0_ADDR_REG is in using, we write the address to FB0_ADDR_REG,
 * if FB1_ADDR_REG is in using, we write the address to FB1_ADDR_REG.
 */
#define CFG_PAGE_FLIP                   BIT(7)
#define CFG_OUTPUT_ENABLE               BIT(8)
#define CFG_HW_CLONE                    BIT(9)
/* Indicate witch fb addr reg is in using, currently. read only */
#define FB_REG_IN_USING                 BIT(11)
#define CFG_GAMMA_EN                    BIT(12)

/* The DC get soft reset if this bit changed from "1" to "0", active low */
#define CFG_RESET_N                     BIT(20)
/* If this bit is set, it say that the CRTC stop working anymore, anchored. */
#define CRTC_ANCHORED                   BIT(24)

/*
 * The DMA step of the DC in LS7A2000/LS2K2000 is configurable,
 * setting those bits on ls7a1000 platform make no effect.
 */
#define CFG_DMA_STEP_MASK              GENMASK(17, 16)
#define CFG_DMA_STEP_SHIFT             16
enum lsdc_dma_steps {
	LSDC_DMA_STEP_256_BYTES = 0,
	LSDC_DMA_STEP_128_BYTES = 1,
	LSDC_DMA_STEP_64_BYTES = 2,
	LSDC_DMA_STEP_32_BYTES = 3,
};

#define CFG_VALID_BITS_MASK             GENMASK(20, 0)

/* For LSDC_CRTCx_HSYNC_REG */
#define HSYNC_INV                       BIT(31)
#define HSYNC_EN                        BIT(30)
#define HSYNC_END_MASK                  GENMASK(28, 16)
#define HSYNC_END_SHIFT                 16
#define HSYNC_START_MASK                GENMASK(12, 0)

Annotation

Implementation Notes