drivers/gpu/drm/mediatek/mtk_dp_reg.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/mediatek/mtk_dp_reg.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/mediatek/mtk_dp_reg.h
Extension
.h
Size
16011 bytes
Lines
363
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _MTK_DP_REG_H_
#define _MTK_DP_REG_H_

#define SEC_OFFSET	0x4000

#define MTK_DP_HPD_DISCONNECT		BIT(1)
#define MTK_DP_HPD_CONNECT		BIT(2)
#define MTK_DP_HPD_INTERRUPT		BIT(3)

/* offset: 0x0 */
#define DP_PHY_GLB_BIAS_GEN_00		0x0
#define RG_XTP_GLB_BIAS_INTR_CTRL		GENMASK(20, 16)
#define DP_PHY_GLB_DPAUX_TX		0x8
#define RG_CKM_PT0_CKTX_IMPSEL			GENMASK(23, 20)
#define MTK_DP_0034			0x34
#define DA_XTP_GLB_CKDET_EN_FORCE_VAL		BIT(15)
#define DA_XTP_GLB_CKDET_EN_FORCE_EN		BIT(14)
#define DA_CKM_INTCKTX_EN_FORCE_VAL		BIT(13)
#define DA_CKM_INTCKTX_EN_FORCE_EN		BIT(12)
#define DA_CKM_CKTX0_EN_FORCE_VAL		BIT(11)
#define DA_CKM_CKTX0_EN_FORCE_EN		BIT(10)
#define DA_CKM_XTAL_CK_FORCE_VAL		BIT(9)
#define DA_CKM_XTAL_CK_FORCE_EN			BIT(8)
#define DA_CKM_BIAS_LPF_EN_FORCE_VAL		BIT(7)
#define DA_CKM_BIAS_LPF_EN_FORCE_EN		BIT(6)
#define DA_CKM_BIAS_EN_FORCE_VAL		BIT(5)
#define DA_CKM_BIAS_EN_FORCE_EN			BIT(4)
#define DA_XTP_GLB_AVD10_ON_FORCE_VAL		BIT(3)
#define DA_XTP_GLB_AVD10_ON_FORCE		BIT(2)
#define DA_XTP_GLB_LDO_EN_FORCE_VAL		BIT(1)
#define DA_XTP_GLB_LDO_EN_FORCE_EN		BIT(0)
#define DP_PHY_LANE_TX_0		0x104
#define RG_XTP_LN0_TX_IMPSEL_PMOS		GENMASK(15, 12)
#define RG_XTP_LN0_TX_IMPSEL_NMOS		GENMASK(19, 16)
#define DP_PHY_LANE_TX_1		0x204
#define RG_XTP_LN1_TX_IMPSEL_PMOS		GENMASK(15, 12)
#define RG_XTP_LN1_TX_IMPSEL_NMOS		GENMASK(19, 16)
#define DP_PHY_LANE_TX_2		0x304
#define RG_XTP_LN2_TX_IMPSEL_PMOS		GENMASK(15, 12)
#define RG_XTP_LN2_TX_IMPSEL_NMOS		GENMASK(19, 16)
#define DP_PHY_LANE_TX_3		0x404
#define RG_XTP_LN3_TX_IMPSEL_PMOS		GENMASK(15, 12)
#define RG_XTP_LN3_TX_IMPSEL_NMOS		GENMASK(19, 16)
#define MTK_DP_1040			0x1040
#define RG_DPAUX_RX_VALID_DEGLITCH_EN		BIT(2)
#define RG_XTP_GLB_CKDET_EN			BIT(1)
#define RG_DPAUX_RX_EN				BIT(0)

/* offset: TOP_OFFSET (0x2000) */
#define MTK_DP_TOP_PWR_STATE		0x2000
#define DP_PWR_STATE_MASK			GENMASK(1, 0)
#define DP_PWR_STATE_BANDGAP			BIT(0)
#define DP_PWR_STATE_BANDGAP_TPLL		BIT(1)
#define DP_PWR_STATE_BANDGAP_TPLL_LANE		GENMASK(1, 0)
#define MTK_DP_TOP_SWING_EMP		0x2004
#define DP_TX0_VOLT_SWING_MASK			GENMASK(1, 0)
#define DP_TX0_VOLT_SWING_SHIFT			0
#define DP_TX0_PRE_EMPH_MASK			GENMASK(3, 2)
#define DP_TX0_PRE_EMPH_SHIFT			2
#define DP_TX1_VOLT_SWING_MASK			GENMASK(9, 8)
#define DP_TX1_VOLT_SWING_SHIFT			8
#define DP_TX1_PRE_EMPH_MASK			GENMASK(11, 10)
#define DP_TX2_VOLT_SWING_MASK			GENMASK(17, 16)
#define DP_TX2_PRE_EMPH_MASK			GENMASK(19, 18)
#define DP_TX3_VOLT_SWING_MASK			GENMASK(25, 24)
#define DP_TX3_PRE_EMPH_MASK			GENMASK(27, 26)
#define MTK_DP_TOP_RESET_AND_PROBE	0x2020
#define SW_RST_B_PHYD				BIT(4)
#define MTK_DP_TOP_IRQ_MASK		0x202c
#define IRQ_MASK_AUX_TOP_IRQ			BIT(2)
#define MTK_DP_TOP_MEM_PD		0x2038
#define MEM_ISO_EN				BIT(0)
#define FUSE_SEL				BIT(2)

/* offset: ENC0_OFFSET (0x3000) */
#define MTK_DP_ENC0_P0_3000			0x3000
#define LANE_NUM_DP_ENC0_P0_MASK			GENMASK(1, 0)
#define VIDEO_MUTE_SW_DP_ENC0_P0			BIT(2)
#define VIDEO_MUTE_SEL_DP_ENC0_P0			BIT(3)
#define ENHANCED_FRAME_EN_DP_ENC0_P0			BIT(4)
#define MTK_DP_ENC0_P0_3004			0x3004
#define VIDEO_M_CODE_SEL_DP_ENC0_P0_MASK		BIT(8)
#define DP_TX_ENCODER_4P_RESET_SW_DP_ENC0_P0		BIT(9)
#define SDP_RESET_SW_DP_ENC0_P0				BIT(13)
#define MTK_DP_ENC0_P0_3010			0x3010
#define HTOTAL_SW_DP_ENC0_P0_MASK			GENMASK(15, 0)
#define MTK_DP_ENC0_P0_3014			0x3014
#define VTOTAL_SW_DP_ENC0_P0_MASK			GENMASK(15, 0)
#define MTK_DP_ENC0_P0_3018			0x3018
#define HSTART_SW_DP_ENC0_P0_MASK			GENMASK(15, 0)

Annotation

Implementation Notes