drivers/gpu/drm/mediatek/mtk_hdmi_regs.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/mediatek/mtk_hdmi_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/mediatek/mtk_hdmi_regs.h
Extension
.h
Size
6903 bytes
Lines
231
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _MTK_HDMI_REGS_H
#define _MTK_HDMI_REGS_H

#define GRL_INT_MASK		0x18
#define GRL_IFM_PORT		0x188
#define GRL_CH_SWAP		0x198
#define LR_SWAP				BIT(0)
#define LFE_CC_SWAP			BIT(1)
#define LSRS_SWAP			BIT(2)
#define RLS_RRS_SWAP			BIT(3)
#define LR_STATUS_SWAP			BIT(4)
#define GRL_I2S_C_STA0		0x140
#define GRL_I2S_C_STA1		0x144
#define GRL_I2S_C_STA2		0x148
#define GRL_I2S_C_STA3		0x14C
#define GRL_I2S_C_STA4		0x150
#define GRL_I2S_UV		0x154
#define I2S_UV_V			BIT(0)
#define I2S_UV_U			BIT(1)
#define I2S_UV_CH_EN_MASK		0x3c
#define I2S_UV_CH_EN(x)			BIT((x) + 2)
#define I2S_UV_TMDS_DEBUG		BIT(6)
#define I2S_UV_NORMAL_INFO_INV		BIT(7)
#define GRL_ACP_ISRC_CTRL	0x158
#define VS_EN				BIT(0)
#define ACP_EN				BIT(1)
#define ISRC1_EN			BIT(2)
#define ISRC2_EN			BIT(3)
#define GAMUT_EN			BIT(4)
#define GRL_CTS_CTRL		0x160
#define CTS_CTRL_SOFT			BIT(0)
#define GRL_INT			0x14
#define INT_MDI				BIT(0)
#define INT_HDCP			BIT(1)
#define INT_FIFO_O			BIT(2)
#define INT_FIFO_U			BIT(3)
#define INT_IFM_ERR			BIT(4)
#define INT_INF_DONE			BIT(5)
#define INT_NCTS_DONE			BIT(6)
#define INT_CTRL_PKT_DONE		BIT(7)
#define GRL_INT_MASK		0x18
#define GRL_CTRL		0x1C
#define CTRL_GEN_EN			BIT(2)
#define CTRL_SPD_EN			BIT(3)
#define CTRL_MPEG_EN			BIT(4)
#define CTRL_AUDIO_EN			BIT(5)
#define CTRL_AVI_EN			BIT(6)
#define CTRL_AVMUTE			BIT(7)
#define	GRL_STATUS		0x20
#define STATUS_HTPLG			BIT(0)
#define STATUS_PORD			BIT(1)
#define GRL_DIVN		0x170
#define NCTS_WRI_ANYTIME		BIT(6)
#define GRL_AUDIO_CFG		0x17C
#define AUDIO_ZERO			BIT(0)
#define HIGH_BIT_RATE			BIT(1)
#define SACD_DST			BIT(2)
#define DST_NORMAL_DOUBLE		BIT(3)
#define DSD_INV				BIT(4)
#define LR_INV				BIT(5)
#define LR_MIX				BIT(6)
#define DSD_SEL				BIT(7)
#define GRL_NCTS		0x184
#define GRL_CH_SW0		0x18C
#define GRL_CH_SW1		0x190
#define GRL_CH_SW2		0x194
#define CH_SWITCH(from, to)		((from) << ((to) * 3))
#define GRL_INFOFRM_VER		0x19C
#define GRL_INFOFRM_TYPE	0x1A0
#define GRL_INFOFRM_LNG		0x1A4
#define GRL_MIX_CTRL		0x1B4
#define MIX_CTRL_SRC_EN			BIT(0)
#define BYPASS_VOLUME			BIT(1)
#define MIX_CTRL_FLAT			BIT(7)
#define GRL_AOUT_CFG		0x1C4
#define AOUT_BNUM_SEL_MASK		0x03
#define AOUT_24BIT			0x00
#define AOUT_20BIT			0x02
#define AOUT_16BIT			0x03
#define AOUT_FIFO_ADAP_CTRL		BIT(6)
#define AOUT_BURST_PREAMBLE_EN		BIT(7)
#define HIGH_BIT_RATE_PACKET_ALIGN	(AOUT_BURST_PREAMBLE_EN | \
					 AOUT_FIFO_ADAP_CTRL)
#define GRL_SHIFT_L1		0x1C0
#define GRL_SHIFT_R2		0x1B0
#define AUDIO_PACKET_OFF		BIT(6)
#define GRL_CFG0		0x24
#define CFG0_I2S_MODE_MASK		0x3
#define CFG0_I2S_MODE_RTJ		0x1
#define CFG0_I2S_MODE_LTJ		0x0

Annotation

Implementation Notes