drivers/gpu/drm/meson/meson_drv.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/meson/meson_drv.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/meson/meson_drv.h
Extension
.h
Size
4335 bytes
Lines
186
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct meson_drm_match_data {
	enum vpu_compatible compat;
	struct meson_afbcd_ops *afbcd_ops;
};

struct meson_drm_soc_limits {
	unsigned long long max_hdmi_phy_freq;
};

struct meson_drm {
	struct device *dev;
	enum vpu_compatible compat;
	void __iomem *io_base;
	struct regmap *hhi;
	int vsync_irq;

	struct meson_canvas *canvas;
	u8 canvas_id_osd1;
	u8 canvas_id_vd1_0;
	u8 canvas_id_vd1_1;
	u8 canvas_id_vd1_2;

	struct drm_device *drm;
	struct drm_crtc *crtc;
	struct drm_plane *primary_plane;
	struct drm_plane *overlay_plane;
	void *encoders[MESON_ENC_LAST];

	const struct meson_drm_soc_limits *limits;

	/* Components Data */
	struct {
		bool osd1_enabled;
		bool osd1_interlace;
		bool osd1_commit;
		bool osd1_afbcd;
		uint32_t osd1_ctrl_stat;
		uint32_t osd1_ctrl_stat2;
		uint32_t osd1_blk0_cfg[5];
		uint32_t osd1_blk1_cfg4;
		uint32_t osd1_blk2_cfg4;
		uint32_t osd1_addr;
		uint32_t osd1_stride;
		uint32_t osd1_height;
		uint32_t osd1_width;
		uint32_t osd_sc_ctrl0;
		uint32_t osd_sc_i_wh_m1;
		uint32_t osd_sc_o_h_start_end;
		uint32_t osd_sc_o_v_start_end;
		uint32_t osd_sc_v_ini_phase;
		uint32_t osd_sc_v_phase_step;
		uint32_t osd_sc_h_ini_phase;
		uint32_t osd_sc_h_phase_step;
		uint32_t osd_sc_h_ctrl0;
		uint32_t osd_sc_v_ctrl0;
		uint32_t osd_blend_din0_scope_h;
		uint32_t osd_blend_din0_scope_v;
		uint32_t osb_blend0_size;
		uint32_t osb_blend1_size;

		bool vd1_enabled;
		bool vd1_commit;
		bool vd1_afbc;
		unsigned int vd1_planes;
		uint32_t vd1_if0_gen_reg;
		uint32_t vd1_if0_luma_x0;
		uint32_t vd1_if0_luma_y0;
		uint32_t vd1_if0_chroma_x0;
		uint32_t vd1_if0_chroma_y0;
		uint32_t vd1_if0_repeat_loop;
		uint32_t vd1_if0_luma0_rpt_pat;
		uint32_t vd1_if0_chroma0_rpt_pat;
		uint32_t vd1_range_map_y;
		uint32_t vd1_range_map_cb;
		uint32_t vd1_range_map_cr;
		uint32_t viu_vd1_fmt_w;
		uint32_t vd1_if0_canvas0;
		uint32_t vd1_if0_gen_reg2;
		uint32_t viu_vd1_fmt_ctrl;
		uint32_t vd1_addr0;
		uint32_t vd1_addr1;
		uint32_t vd1_addr2;
		uint32_t vd1_stride0;
		uint32_t vd1_stride1;
		uint32_t vd1_stride2;
		uint32_t vd1_height0;
		uint32_t vd1_height1;
		uint32_t vd1_height2;
		uint32_t vd1_afbc_mode;
		uint32_t vd1_afbc_en;

Annotation

Implementation Notes