drivers/gpu/drm/meson/meson_dw_hdmi.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/meson/meson_dw_hdmi.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/meson/meson_dw_hdmi.h
Extension
.h
Size
6272 bytes
Lines
161
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __MESON_DW_HDMI_H
#define __MESON_DW_HDMI_H

/*
 * Bit 15-10: RW Reserved. Default 1 starting from G12A
 * Bit 9 RW sw_reset_i2c starting from G12A
 * Bit 8 RW sw_reset_axiarb starting from G12A
 * Bit 7 RW Reserved. Default 1, sw_reset_emp starting from G12A
 * Bit 6 RW Reserved. Default 1, sw_reset_flt starting from G12A
 * Bit 5 RW Reserved. Default 1, sw_reset_hdcp22 starting from G12A
 * Bit 4 RW sw_reset_phyif: PHY interface. 1=Apply reset; 0=Release from reset.
 *     Default 1.
 * Bit 3 RW sw_reset_intr: interrupt module. 1=Apply reset;
 *     0=Release from reset.
 *     Default 1.
 * Bit 2 RW sw_reset_mem: KSV/REVOC mem. 1=Apply reset; 0=Release from reset.
 *     Default 1.
 * Bit 1 RW sw_reset_rnd: random number interface to HDCP. 1=Apply reset;
 *     0=Release from reset. Default 1.
 * Bit 0 RW sw_reset_core: connects to IP's ~irstz. 1=Apply reset;
 *     0=Release from reset. Default 1.
 */
#define HDMITX_TOP_SW_RESET                     (0x000)

/*
 * Bit 31 RW free_clk_en: 0=Enable clock gating for power saving; 1= Disable
 * Bit 12 RW i2s_ws_inv:1=Invert i2s_ws; 0=No invert. Default 0.
 * Bit 11 RW i2s_clk_inv: 1=Invert i2s_clk; 0=No invert. Default 0.
 * Bit 10 RW spdif_clk_inv: 1=Invert spdif_clk; 0=No invert. Default 0.
 * Bit 9 RW tmds_clk_inv: 1=Invert tmds_clk; 0=No invert. Default 0.
 * Bit 8 RW pixel_clk_inv: 1=Invert pixel_clk; 0=No invert. Default 0.
 * Bit 7 RW hdcp22_skpclk_en: starting from G12A, 1=enable; 0=disable
 * Bit 6 RW hdcp22_esmclk_en: starting from G12A, 1=enable; 0=disable
 * Bit 5 RW hdcp22_tmdsclk_en: starting from G12A, 1=enable; 0=disable
 * Bit 4 RW cec_clk_en: 1=enable cec_clk; 0=disable. Default 0. Reserved for G12A
 * Bit 3 RW i2s_clk_en: 1=enable i2s_clk; 0=disable. Default 0.
 * Bit 2 RW spdif_clk_en: 1=enable spdif_clk; 0=disable. Default 0.
 * Bit 1 RW tmds_clk_en: 1=enable tmds_clk;  0=disable. Default 0.
 * Bit 0 RW pixel_clk_en: 1=enable pixel_clk; 0=disable. Default 0.
 */
#define HDMITX_TOP_CLK_CNTL                     (0x001)

/*
 * Bit 31:28 RW rxsense_glitch_width: starting from G12A
 * Bit 27:16 RW rxsense_valid_width: starting from G12A
 * Bit 11: 0 RW hpd_valid_width: filter out width <= M*1024.    Default 0.
 * Bit 15:12 RW hpd_glitch_width: filter out glitch <= N.       Default 0.
 */
#define HDMITX_TOP_HPD_FILTER                   (0x002)

/*
 * intr_maskn: MASK_N, one bit per interrupt source.
 *     1=Enable interrupt source; 0=Disable interrupt source. Default 0.
 * [  7] rxsense_fall starting from G12A
 * [  6] rxsense_rise starting from G12A
 * [  5] err_i2c_timeout starting from G12A
 * [  4] hdcp22_rndnum_err
 * [  3] nonce_rfrsh_rise
 * [  2] hpd_fall_intr
 * [  1] hpd_rise_intr
 * [  0] core_intr
 */
#define HDMITX_TOP_INTR_MASKN                   (0x003)

/*
 * Bit 30: 0 RW intr_stat: For each bit, write 1 to manually set the interrupt
 *     bit, read back the interrupt status.
 * Bit    31 R  IP interrupt status
 * Bit     7 RW rxsense_fall starting from G12A
 * Bit     6 RW rxsense_rise starting from G12A
 * Bit     5 RW err_i2c_timeout starting from G12A
 * Bit     2 RW hpd_fall
 * Bit     1 RW hpd_rise
 * Bit     0 RW IP interrupt
 */
#define HDMITX_TOP_INTR_STAT                    (0x004)

/*
 * [7]    rxsense_fall starting from G12A
 * [6]    rxsense_rise starting from G12A
 * [5]    err_i2c_timeout starting from G12A
 * [4]	  hdcp22_rndnum_err
 * [3]	  nonce_rfrsh_rise
 * [2]	  hpd_fall
 * [1]	  hpd_rise
 * [0]	  core_intr_rise
 */
#define HDMITX_TOP_INTR_STAT_CLR                (0x005)

#define HDMITX_TOP_INTR_CORE		BIT(0)

Annotation

Implementation Notes